core_1c6.hier_info

运用TLC5510A高速(20M),扫描出波形,测量相位差,两个TLC5510A测两个波形.

clk => SUM[0].CLK
clk => DATA[18].CLK
H_sum[0] <= SUM[8].DB_MAX_OUTPUT_PORT_TYPE
H_sum[1] <= SUM[9].DB_MAX_OUTPUT_PORT_TYPE
H_sum[2] <= SUM[10].DB_MAX_OUTPUT_PORT_TYPE
H_sum[3] <= SUM[11].DB_MAX_OUTPUT_PORT_TYPE
H_sum[4] <= SUM[12].DB_MAX_OUTPUT_PORT_TYPE
H_sum[5] <= SUM[13].DB_MAX_OUTPUT_PORT_TYPE
H_sum[6] <= SUM[14].DB_MAX_OUTPUT_PORT_TYPE
H_sum[7] <= SUM[15].DB_MAX_OUTPUT_PORT_TYPE
H_sum[8] <= SUM[16].DB_MAX_OUTPUT_PORT_TYPE
H_sum[9] <= SUM[17].DB_MAX_OUTPUT_PORT_TYPE


|core_1c6|fp_2:inst18
C_in => Cout.CLK
C_out <= Cout.DB_MAX_OUTPUT_PORT_TYPE


|core_1c6|fp_2:inst32
C_in => Cout.CLK
C_out <= Cout.DB_MAX_OUTPUT_PORT_TYPE


|core_1c6|data_ctl:inst10
CS => DOUT~0.IN0
WR => DOUT~0.IN1
DIN[0] => DOUT~8.DATAIN
DIN[1] => DOUT~7.DATAIN
DIN[2] => DOUT~6.DATAIN
DIN[3] => DOUT~5.DATAIN
DIN[4] => DOUT~4.DATAIN
DIN[5] => DOUT~3.DATAIN
DIN[6] => DOUT~2.DATAIN
DIN[7] => DOUT~1.DATAIN
DOUT[0] <= DOUT~8.DB_MAX_OUTPUT_PORT_TYPE
DOUT[1] <= DOUT~7.DB_MAX_OUTPUT_PORT_TYPE
DOUT[2] <= DOUT~6.DB_MAX_OUTPUT_PORT_TYPE
DOUT[3] <= DOUT~5.DB_MAX_OUTPUT_PORT_TYPE
DOUT[4] <= DOUT~4.DB_MAX_OUTPUT_PORT_TYPE
DOUT[5] <= DOUT~3.DB_MAX_OUTPUT_PORT_TYPE
DOUT[6] <= DOUT~2.DB_MAX_OUTPUT_PORT_TYPE
DOUT[7] <= DOUT~1.DB_MAX_OUTPUT_PORT_TYPE


|core_1c6|select2_1:inst31
sel => out_q~0.OUTPUTSELECT
sel => out_q~1.OUTPUTSELECT
sel => out_q~2.OUTPUTSELECT
sel => out_q~3.OUTPUTSELECT
sel => out_q~4.OUTPUTSELECT
sel => out_q~5.OUTPUTSELECT
sel => out_q~6.OUTPUTSELECT
sel => out_q~7.OUTPUTSELECT
q1[0] => out_q~7.DATAB
q1[1] => out_q~6.DATAB
q1[2] => out_q~5.DATAB
q1[3] => out_q~4.DATAB
q1[4] => out_q~3.DATAB
q1[5] => out_q~2.DATAB
q1[6] => out_q~1.DATAB
q1[7] => out_q~0.DATAB
q2[0] => out_q~7.DATAA
q2[1] => out_q~6.DATAA
q2[2] => out_q~5.DATAA
q2[3] => out_q~4.DATAA
q2[4] => out_q~3.DATAA
q2[5] => out_q~2.DATAA
q2[6] => out_q~1.DATAA
q2[7] => out_q~0.DATAA
out_q[0] <= out_q~7.DB_MAX_OUTPUT_PORT_TYPE
out_q[1] <= out_q~6.DB_MAX_OUTPUT_PORT_TYPE
out_q[2] <= out_q~5.DB_MAX_OUTPUT_PORT_TYPE
out_q[3] <= out_q~4.DB_MAX_OUTPUT_PORT_TYPE
out_q[4] <= out_q~3.DB_MAX_OUTPUT_PORT_TYPE
out_q[5] <= out_q~2.DB_MAX_OUTPUT_PORT_TYPE
out_q[6] <= out_q~1.DB_MAX_OUTPUT_PORT_TYPE
out_q[7] <= out_q~0.DB_MAX_OUTPUT_PORT_TYPE


|core_1c6|select_q:inst19
sel => temp[7].OUTPUTSELECT
sel => temp[6].OUTPUTSELECT
sel => temp[5].OUTPUTSELECT
sel => temp[4].OUTPUTSELECT
sel => temp[3].OUTPUTSELECT
sel => temp[2].OUTPUTSELECT
sel => temp[1].OUTPUTSELECT
sel => temp[0].OUTPUTSELECT
q1[0] => temp[0].DATAB
q1[1] => temp[1].DATAB
q1[2] => temp[2].DATAB
q1[3] => temp[3].DATAB
q1[4] => temp[4].DATAB
q1[5] => temp[5].DATAB
q1[6] => temp[6].DATAB
q1[7] => temp[7].DATAB
q2[0] => temp[0].DATAA
q2[1] => temp[1].DATAA
q2[2] => temp[2].DATAA
q2[3] => temp[3].DATAA
q2[4] => temp[4].DATAA
q2[5] => temp[5].DATAA
q2[6] => temp[6].DATAA
q2[7] => temp[7].DATAA
clk => out_q[6]~reg0.CLK
clk => out_q[5]~reg0.CLK
clk => out_q[4]~reg0.CLK
clk => out_q[3]~reg0.CLK
clk => out_q[2]~reg0.CLK
clk => out_q[1]~reg0.CLK
clk => out_q[0]~reg0.CLK
clk => out_q[7]~reg0.CLK
out_q[0] <= out_q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_q[1] <= out_q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_q[2] <= out_q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_q[3] <= out_q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_q[4] <= out_q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_q[5] <= out_q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_q[6] <= out_q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_q[7] <= out_q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|core_1c6|fp_2:inst26
C_in => Cout.CLK
C_out <= Cout.DB_MAX_OUTPUT_PORT_TYPE


|core_1c6|fp_2:inst25
C_in => Cout.CLK
C_out <= Cout.DB_MAX_OUTPUT_PORT_TYPE


|core_1c6|fp_2:inst22
C_in => Cout.CLK
C_out <= Cout.DB_MAX_OUTPUT_PORT_TYPE


|core_1c6|select2_1:inst8
sel => out_q~0.OUTPUTSELECT
sel => out_q~1.OUTPUTSELECT
sel => out_q~2.OUTPUTSELECT
sel => out_q~3.OUTPUTSELECT
sel => out_q~4.OUTPUTSELECT
sel => out_q~5.OUTPUTSELECT
sel => out_q~6.OUTPUTSELECT
sel => out_q~7.OUTPUTSELECT
q1[0] => out_q~7.DATAB
q1[1] => out_q~6.DATAB
q1[2] => out_q~5.DATAB
q1[3] => out_q~4.DATAB
q1[4] => out_q~3.DATAB
q1[5] => out_q~2.DATAB
q1[6] => out_q~1.DATAB
q1[7] => out_q~0.DATAB
q2[0] => out_q~7.DATAA
q2[1] => out_q~6.DATAA
q2[2] => out_q~5.DATAA
q2[3] => out_q~4.DATAA
q2[4] => out_q~3.DATAA
q2[5] => out_q~2.DATAA
q2[6] => out_q~1.DATAA
q2[7] => out_q~0.DATAA
out_q[0] <= out_q~7.DB_MAX_OUTPUT_PORT_TYPE
out_q[1] <= out_q~6.DB_MAX_OUTPUT_PORT_TYPE
out_q[2] <= out_q~5.DB_MAX_OUTPUT_PORT_TYPE
out_q[3] <= out_q~4.DB_MAX_OUTPUT_PORT_TYPE
out_q[4] <= out_q~3.DB_MAX_OUTPUT_PORT_TYPE
out_q[5] <= out_q~2.DB_MAX_OUTPUT_PORT_TYPE
out_q[6] <= out_q~1.DB_MAX_OUTPUT_PORT_TYPE
out_q[7] <= out_q~0.DB_MAX_OUTPUT_PORT_TYPE


|core_1c6|RAM_1K:inst5
data[0] => data[0]~7.IN1
data[1] => data[1]~6.IN1
data[2] => data[2]~5.IN1
data[3] => data[3]~4.IN1
data[4] => data[4]~3.IN1
data[5] => data[5]~2.IN1
data[6] => data[6]~1.IN1
data[7] => data[7]~0.IN1
wren => wren~0.IN1
wraddress[0] => wraddress[0]~9.IN1
wraddress[1] => wraddress[1]~8.IN1
wraddress[2] => wraddress[2]~7.IN1
wraddress[3] => wraddress[3]~6.IN1
wraddress[4] => wraddress[4]~5.IN1
wraddress[5] => wraddress[5]~4.IN1
wraddress[6] => wraddress[6]~3.IN1
wraddress[7] => wraddress[7]~2.IN1
wraddress[8] => wraddress[8]~1.IN1
wraddress[9] => wraddress[9]~0.IN1
rdaddress[0] => rdaddress[0]~9.IN1
rdaddress[1] => rdaddress[1]~8.IN1
rdaddress[2] => rdaddress[2]~7.IN1
rdaddress[3] => rdaddress[3]~6.IN1
rdaddress[4] => rdaddress[4]~5.IN1
rdaddress[5] => rdaddress[5]~4.IN1
rdaddress[6] => rdaddress[6]~3.IN1
rdaddress[7] => rdaddress[7]~2.IN1
rdaddress[8] => rdaddress[8]~1.IN1
rdaddress[9] => rdaddress[9]~0.IN1
rden => rden~0.IN1
wrclock => wrclock~0.IN1
rdclock => rdclock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_b
q[1] <= altsyncram:altsyncram_component.q_b
q[2] <= altsyncram:altsyncram_component.q_b
q[3] <= altsyncram:altsyncram_component.q_b
q[4] <= altsyncram:altsyncram_component.q_b
q[5] <= altsyncram:altsyncram_component.q_b
q[6] <= altsyncram:altsyncram_component.q_b
q[7] <= altsyncram:altsyncram_component.q_b


|core_1c6|RAM_1K:inst5|altsyncram:altsyncram_component
wren_a => altsyncram_aqb1:auto_generated.wren_a
wren_b => ~NO_FANOUT~
rden_b => altsyncram_aqb1:auto_generated.rden_b
data_a[0] => altsyncram_aqb1:auto_generated.data_a[0]
data_a[1] => altsyncram_aqb1:auto_generated.data_a[1]
data_a[2] => altsyncram_aqb1:auto_generated.data_a[2]
data_a[3] => altsyncram_aqb1:auto_generated.data_a[3]
data_a[4] => altsyncram_aqb1:auto_generated.data_a[4]
data_a[5] => altsyncram_aqb1:auto_generated.data_a[5]
data_a[6] => altsyncram_aqb1:auto_generated.data_a[6]
data_a[7] => altsyncram_aqb1:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
address_a[0] => altsyncram_aqb1:auto_generated.address_a[0]
address_a[1] => altsyncram_aqb1:auto_generated.address_a[1]
address_a[2] => altsyncram_aqb1:auto_generated.address_a[2]
address_a[3] => altsyncram_aqb1:auto_generated.address_a[3]
address_a[4] => altsyncram_aqb1:auto_generated.address_a[4]
address_a[5] => altsyncram_aqb1:auto_generated.address_a[5]
address_a[6] => altsyncram_aqb1:auto_generated.address_a[6]
address_a[7] => altsyncram_aqb1:auto_generated.address_a[7]
address_a[8] => altsyncram_aqb1:auto_generated.address_a[8]
address_a[9] => altsyncram_aqb1:auto_generated.address_a[9]
address_b[0] => altsyncram_aqb1:auto_generated.address_b[0]
address_b[1] => altsyncram_aqb1:auto_generated.address_b[1]
address_b[2] => altsyncram_aqb1:auto_generated.address_b[2]
address_b[3] => altsyncram_aqb1:auto_generated.address_b[3]
address_b[4] => altsyncram_aqb1:auto_generated.address_b[4]
address_b[5] => altsyncram_aqb1:auto_generated.address_b[5]
address_b[6] => altsyncram_aqb1:auto_generated.address_b[6]
address_b[7] => altsyncram_aqb1:auto_generated.address_b[7]
address_b[8] => altsyncram_aqb1:auto_generated.address_b[8]
address_b[9] => altsyncram_aqb1:auto_generated.address_b[9]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_aqb1:auto_generated.clock0
clock1 => altsyncram_aqb1:auto_generated.clock1
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= <GND>
q_a[1] <= <GND>
q_a[2] <= <GND>
q_a[3] <= <GND>
q_a[4] <= <GND>
q_a[5] <= <GND>
q_a[6] <= <GND>
q_a[7] <= <GND>
q_b[0] <= altsyncram_aqb1:auto_generated.q_b[0]
q_b[1] <= altsyncram_aqb1:auto_generated.q_b[1]
q_b[2] <= altsyncram_aqb1:auto_generated.q_b[2]
q_b[3] <= altsyncram_aqb1:auto_generated.q_b[3]
q_b[4] <= altsyncram_aqb1:auto_generated.q_b[4]
q_b[5] <= altsyncram_aqb1:auto_generated.q_b[5]
q_b[6] <= altsyncram_aqb1:auto_generated.q_b[6]
q_b[7] <= altsyncram_aqb1:auto_generated.q_b[7]


|core_1c6|RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9