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📄 core_1c6.map.qmsg

📁 运用TLC5510A高速(20M),扫描出波形,测量相位差,两个TLC5510A测两个波形.
💻 QMSG
📖 第 1 页 / 共 5 页
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{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add18:inst47\|DATA\[15\] data_in GND " "Warning: Reduced register \"add18:inst47\|DATA\[15\]\" with stuck data_in port to stuck value GND" {  } { { "add18.v" "" { Text "D:/Test_Phase/cexiang1/add18.v" 20 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add18:inst47\|DATA\[14\] data_in GND " "Warning: Reduced register \"add18:inst47\|DATA\[14\]\" with stuck data_in port to stuck value GND" {  } { { "add18.v" "" { Text "D:/Test_Phase/cexiang1/add18.v" 20 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add18:inst47\|DATA\[13\] data_in GND " "Warning: Reduced register \"add18:inst47\|DATA\[13\]\" with stuck data_in port to stuck value GND" {  } { { "add18.v" "" { Text "D:/Test_Phase/cexiang1/add18.v" 20 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add18:inst47\|DATA\[12\] data_in GND " "Warning: Reduced register \"add18:inst47\|DATA\[12\]\" with stuck data_in port to stuck value GND" {  } { { "add18.v" "" { Text "D:/Test_Phase/cexiang1/add18.v" 20 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add18:inst47\|DATA\[11\] data_in GND " "Warning: Reduced register \"add18:inst47\|DATA\[11\]\" with stuck data_in port to stuck value GND" {  } { { "add18.v" "" { Text "D:/Test_Phase/cexiang1/add18.v" 20 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add18:inst47\|DATA\[10\] data_in GND " "Warning: Reduced register \"add18:inst47\|DATA\[10\]\" with stuck data_in port to stuck value GND" {  } { { "add18.v" "" { Text "D:/Test_Phase/cexiang1/add18.v" 20 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add18:inst47\|DATA\[9\] data_in GND " "Warning: Reduced register \"add18:inst47\|DATA\[9\]\" with stuck data_in port to stuck value GND" {  } { { "add18.v" "" { Text "D:/Test_Phase/cexiang1/add18.v" 20 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add18:inst47\|DATA\[8\] data_in GND " "Warning: Reduced register \"add18:inst47\|DATA\[8\]\" with stuck data_in port to stuck value GND" {  } { { "add18.v" "" { Text "D:/Test_Phase/cexiang1/add18.v" 20 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add18:inst47\|DATA\[18\] data_in GND " "Warning: Reduced register \"add18:inst47\|DATA\[18\]\" with stuck data_in port to stuck value GND" {  } { { "add18.v" "" { Text "D:/Test_Phase/cexiang1/add18.v" 20 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "ce_gao:inst12\|data\[7\] " "Warning: Converting TRI node \"ce_gao:inst12\|data\[7\]\" that feeds logic to a wire" {  } { { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 5 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "ce_gao:inst12\|data\[6\] " "Warning: Converting TRI node \"ce_gao:inst12\|data\[6\]\" that feeds logic to a wire" {  } { { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 5 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "ce_gao:inst12\|data\[5\] " "Warning: Converting TRI node \"ce_gao:inst12\|data\[5\]\" that feeds logic to a wire" {  } { { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 5 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "ce_gao:inst12\|data\[4\] " "Warning: Converting TRI node \"ce_gao:inst12\|data\[4\]\" that feeds logic to a wire" {  } { { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 5 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "ce_gao:inst12\|data\[3\] " "Warning: Converting TRI node \"ce_gao:inst12\|data\[3\]\" that feeds logic to a wire" {  } { { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 5 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "ce_gao:inst12\|data\[2\] " "Warning: Converting TRI node \"ce_gao:inst12\|data\[2\]\" that feeds logic to a wire" {  } { { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 5 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "ce_gao:inst12\|data\[1\] " "Warning: Converting TRI node \"ce_gao:inst12\|data\[1\]\" that feeds logic to a wire" {  } { { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 5 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "ce_gao:inst12\|data\[0\] " "Warning: Converting TRI node \"ce_gao:inst12\|data\[0\]\" that feeds logic to a wire" {  } { { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 5 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "ScanKey:inst15\|Dout\[7\] " "Warning: Converting TRI node \"ScanKey:inst15\|Dout\[7\]\" that feeds logic to a wire" {  } { { "scankey.v" "" { Text "D:/Test_Phase/cexiang1/scankey.v" 9 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "ScanKey:inst15\|Dout\[6\] " "Warning: Converting TRI node \"ScanKey:inst15\|Dout\[6\]\" that feeds logic to a wire" {  } { { "scankey.v" "" { Text "D:/Test_Phase/cexiang1/scankey.v" 9 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "ScanKey:inst15\|Dout\[5\] " "Warning: Converting TRI node \"ScanKey:inst15\|Dout\[5\]\" that feeds logic to a wire" {  } { { "scankey.v" "" { Text "D:/Test_Phase/cexiang1/scankey.v" 9 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "ScanKey:inst15\|Dout\[4\] " "Warning: Converting TRI node \"ScanKey:inst15\|Dout\[4\]\" that feeds logic to a wire" {  } { { "scankey.v" "" { Text "D:/Test_Phase/cexiang1/scankey.v" 9 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "ScanKey:inst15\|Dout\[3\] " "Warning: Converting TRI node \"ScanKey:inst15\|Dout\[3\]\" that feeds logic to a wire" {  } { { "scankey.v" "" { Text "D:/Test_Phase/cexiang1/scankey.v" 9 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "ScanKey:inst15\|Dout\[2\] " "Warning: Converting TRI node \"ScanKey:inst15\|Dout\[2\]\" that feeds logic to a wire" {  } { { "scankey.v" "" { Text "D:/Test_Phase/cexiang1/scankey.v" 9 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "ScanKey:inst15\|Dout\[1\] " "Warning: Converting TRI node \"ScanKey:inst15\|Dout\[1\]\" that feeds logic to a wire" {  } { { "scankey.v" "" { Text "D:/Test_Phase/cexiang1/scankey.v" 9 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "ScanKey:inst15\|Dout\[0\] " "Warning: Converting TRI node \"ScanKey:inst15\|Dout\[0\]\" that feeds logic to a wire" {  } { { "scankey.v" "" { Text "D:/Test_Phase/cexiang1/scankey.v" 9 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0}  } {  } 0 0 "Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "ScanKey:inst15\|KC_out\[1\] ScanKey:inst15\|KC_out\[2\] " "Info: Duplicate register \"ScanKey:inst15\|KC_out\[1\]\" merged to single register \"ScanKey:inst15\|KC_out\[2\]\"" {  } { { "scankey.v" "" { Text "D:/Test_Phase/cexiang1/scankey.v" 61 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ScanKey:inst15\|KC_out\[0\] ScanKey:inst15\|KC_out\[2\] " "Info: Duplicate register \"ScanKey:inst15\|KC_out\[0\]\" merged to single register \"ScanKey:inst15\|KC_out\[2\]\"" {  } { { "scankey.v" "" { Text "D:/Test_Phase/cexiang1/scankey.v" 61 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ScanKey:inst15\|KR_out\[2\] ScanKey:inst15\|KR_out\[5\] " "Info: Duplicate register \"ScanKey:inst15\|KR_out\[2\]\" merged to single register \"ScanKey:inst15\|KR_out\[5\]\"" {  } { { "scankey.v" "" { Text "D:/Test_Phase/cexiang1/scankey.v" 61 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ScanKey:inst15\|KR_out\[0\] ScanKey:inst15\|KR_out\[5\] " "Info: Duplicate register \"ScanKey:inst15\|KR_out\[0\]\" merged to single register \"ScanKey:inst15\|KR_out\[5\]\"" {  } { { "scankey.v" "" { Text "D:/Test_Phase/cexiang1/scankey.v" 61 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ScanKey:inst15\|KR_out\[3\] ScanKey:inst15\|KR_out\[5\] " "Info: Duplicate register \"ScanKey:inst15\|KR_out\[3\]\" merged to single register \"ScanKey:inst15\|KR_out\[5\]\"" {  } { { "scankey.v" "" { Text "D:/Test_Phase/cexiang1/scankey.v" 61 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ScanKey:inst15\|KR_out\[4\] ScanKey:inst15\|KR_out\[5\] " "Info: Duplicate register \"ScanKey:inst15\|KR_out\[4\]\" merged to single register \"ScanKey:inst15\|KR_out\[5\]\"" {  } { { "scankey.v" "" { Text "D:/Test_Phase/cexiang1/scankey.v" 61 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ScanKey:inst15\|KR_out\[1\] ScanKey:inst15\|KR_out\[5\] " "Info: Duplicate register \"ScanKey:inst15\|KR_out\[1\]\" merged to single register \"ScanKey:inst15\|KR_out\[5\]\"" {  } { { "scankey.v" "" { Text "D:/Test_Phase/cexiang1/scankey.v" 61 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_ALTSYNCRAM_ROM_INFERRED" "ScanKey:inst15\|reduce_or~16 512 5 " "Info: Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=512, WIDTH_A=5) from the following design logic: \"ScanKey:inst15\|reduce_or~16\"" {  } {  } 0 0 "Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=%2!d!, WIDTH_A=%3!d!) from the following design logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_r9l.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_r9l.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_r9l " "Info: Found entity 1: altsyncram_r9l" {  } { { "db/altsyncram_r9l.tdf" "" { Text "D:/Test_Phase/cexiang1/db/altsyncram_r9l.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_HDR" "" "Info: One or more bidirs are fed by always enabled tri-state buffers" { { "Info" "IOPT_MLS_FANOUT_MOVED_FOR_PERMANENTLY_ENABLED_TRI_SUB" "P1\[5\] " "Info: Fan-out of permanently enabled tri-state buffer feeding bidir \"P1\[5\]\" is moved to its source" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 816 -376 -200 832 "P1\[7..0\]" "" } { 1384 120 184 1400 "P1\[0\]" "" } { 864 632 720 880 "P1\[3\]" "" } { 1760 864 928 1776 "P1\[5\]" "" } { 976 840 888 992 "P1\[6\]" "" } { 1008 536 576 1024 "P1\[3\]" "" } { 1408 456 512 1424 "P1\[0\]" "" } { 1144 840 875 1160 "P1\[5\]" "" } { 1192 608 688 1208 "P1\[5\]" "" } { 976 -72 -24 992 "P1\[5\]" "" } { 1176 -104 -16 1192 "P1\[5\]" "" } { 1280 472 520 1296 "P1\[4\]" "" } { 1584 40 112 1600 "P1\[2\]" "" } } } }  } 0 0 "Fan-out of permanently enabled tri-state buffer feeding bidir \"%1!s!\" is moved to its source" 0 0}  } {  } 0 0 "One or more bidirs are fed by always enabled tri-state buffers" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "BUS_Connect:inst9\|Data_Temp\[7\] " "Warning: Latch BUS_Connect:inst9\|Data_Temp\[7\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA P2\[7\] " "Warning: Ports D and ENA on the latch are fed by the same signal P2\[7\]" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 344 -8 160 360 "P2\[7..0\]" "" } { 264 488 523 280 "P2\[1\]" "" } { 376 200 248 392 "P2\[7\]" "" } { 392 208 248 408 "P2\[6..3\]" "" } { 680 336 392 696 "P2\[6..0\]" "" } { 1632 40 112 1648 "P2\[1..0\]" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 16 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "BUS_Connect:inst9\|Data_Temp\[6\] " "Warning: Latch BUS_Connect:inst9\|Data_Temp\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA P2\[7\] " "Warning: Ports D and ENA on the latch are fed by the same signal P2\[7\]" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 344 -8 160 360 "P2\[7..0\]" "" } { 264 488 523 280 "P2\[1\]" "" } { 376 200 248 392 "P2\[7\]" "" } { 392 208 248 408 "P2\[6..3\]" "" } { 680 336 392 696 "P2\[6..0\]" "" } { 1632 40 112 1648 "P2\[1..0\]" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 16 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "BUS_Connect:inst9\|Data_Temp\[5\] " "Warning: Latch BUS_Connect:inst9\|Data_Temp\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA P2\[7\] " "Warning: Ports D and ENA on the latch are fed by the same signal P2\[7\]" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 344 -8 160 360 "P2\[7..0\]" "" } { 264 488 523 280 "P2\[1\]" "" } { 376 200 248 392 "P2\[7\]" "" } { 392 208 248 408 "P2\[6..3\]" "" } { 680 336 392 696 "P2\[6..0\]" "" } { 1632 40 112 1648 "P2\[1..0\]" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 16 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "BUS_Connect:inst9\|Data_Temp\[4\] " "Warning: Latch BUS_Connect:inst9\|Data_Temp\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA P2\[7\] " "Warning: Ports D and ENA on the latch are fed by the same signal P2\[7\]" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 344 -8 160 360 "P2\[7..0\]" "" } { 264 488 523 280 "P2\[1\]" "" } { 376 200 248 392 "P2\[7\]" "" } { 392 208 248 408 "P2\[6..3\]" "" } { 680 336 392 696 "P2\[6..0\]" "" } { 1632 40 112 1648 "P2\[1..0\]" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 16 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "BUS_Connect:inst9\|Data_Temp\[3\] " "Warning: Latch BUS_Connect:inst9\|Data_Temp\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA P2\[7\] " "Warning: Ports D and ENA on the latch are fed by the same signal P2\[7\]" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 344 -8 160 360 "P2\[7..0\]" "" } { 264 488 523 280 "P2\[1\]" "" } { 376 200 248 392 "P2\[7\]" "" } { 392 208 248 408 "P2\[6..3\]" "" } { 680 336 392 696 "P2\[6..0\]" "" } { 1632 40 112 1648 "P2\[1..0\]" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 16 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "BUS_Connect:inst9\|Data_Temp\[2\] " "Warning: Latch BUS_Connect:inst9\|Data_Temp\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA P2\[7\] " "Warning: Ports D and ENA on the latch are fed by the same signal P2\[7\]" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 344 -8 160 360 "P2\[7..0\]" "" } { 264 488 523 280 "P2\[1\]" "" } { 376 200 248 392 "P2\[7\]" "" } { 392 208 248 408 "P2\[6..3\]" "" } { 680 336 392 696 "P2\[6..0\]" "" } { 1632 40 112 1648 "P2\[1..0\]" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 16 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "BUS_Connect:inst9\|Data_Temp\[1\] " "Warning: Latch BUS_Connect:inst9\|Data_Temp\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA P2\[7\] " "Warning: Ports D and ENA on the latch are fed by the same signal P2\[7\]" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 344 -8 160 360 "P2\[7..0\]" "" } { 264 488 523 280 "P2\[1\]" "" } { 376 200 248 392 "P2\[7\]" "" } { 392 208 248 408 "P2\[6..3\]" "" } { 680 336 392 696 "P2\[6..0\]" "" } { 1632 40 112 1648 "P2\[1..0\]" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 16 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "BUS_Connect:inst9\|Data_Temp\[0\] " "Warning: Latch BUS_Connect:inst9\|Data_Temp\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA P2\[7\] " "Warning: Ports D and ENA on the latch are fed by the same signal P2\[7\]" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 344 -8 160 360 "P2\[7..0\]" "" } { 264 488 523 280 "P2\[1\]" "" } { 376 200 248 392 "P2\[7\]" "" } { 392 208 248 408 "P2\[6..3\]" "" } { 680 336 392 696 "P2\[6..0\]" "" } { 1632 40 112 1648 "P2\[1..0\]" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 16 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_ENABLED_OE" "" "Warning: TRI or OPNDRN buffers permanently enabled" { { "Warning" "WOPT_MLS_NODE_NAME" "P1\[5\]~13 " "Warning: Node \"P1\[5\]~13\"" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 816 -376 -200 832 "P1\[7..0\]" "" } { 1384 120 184 1400 "P1\[0\]" "" } { 864 632 720 880 "P1\[3\]" "" } { 1760 864 928 1776 "P1\[5\]" "" } { 976 840 888 992 "P1\[6\]" "" } { 1008 536 576 1024 "P1\[3\]" "" } { 1408 456 512 1424 "P1\[0\]" "" } { 1144 840 875 1160 "P1\[5\]" "" } { 1192 608 688 1208 "P1\[5\]" "" } { 976 -72 -24 992 "P1\[5\]" "" } { 1176 -104 -16 1192 "P1\[5\]" "" } { 1280 472 520 1296 "P1\[4\]" "" } { 1584 40 112 1600 "P1\[2\]" "" } } } }  } 0 0 "Node \"%1!s!\"" 0 0}  } {  } 0 0 "TRI or OPNDRN buffers permanently enabled" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "FS GND " "Warning: Pin \"FS\" stuck at GND" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 464 560 736 480 "FS" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "EA VCC " "Warning: Pin \"EA\" stuck at VCC" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 600 528 704 616 "EA" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LED\[7\] GND " "Warning: Pin \"LED\[7\]\" stuck at GND" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 376 576 752 392 "LED\[7..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LED\[6\] GND " "Warning: Pin \"LED\[6\]\" stuck at GND" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 376 576 752 392 "LED\[7..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LED\[5\] GND " "Warning: Pin \"LED\[5\]\" stuck at GND" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 376 576 752 392 "LED\[7..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LED\[4\] GND " "Warning: Pin \"LED\[4\]\" stuck at GND" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 376 576 752 392 "LED\[7..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LED\[3\] GND " "Warning: Pin \"LED\[3\]\" stuck at GND" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 376 576 752 392 "LED\[7..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LED\[2\] GND " "Warning: Pin \"LED\[2\]\" stuck at GND" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 376 576 752 392 "LED\[7..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LED\[1\] GND " "Warning: Pin \"LED\[1\]\" stuck at GND" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 376 576 752 392 "LED\[7..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LED\[0\] GND " "Warning: Pin \"LED\[0\]\" stuck at GND" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 376 576 752 392 "LED\[7..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "out11 P1\[0\] " "Warning: Output pin \"out11\" driven by bidirectional pin \"P1\[0\]\" cannot be tri-stated" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 1416 872 1048 1432 "out11" "" } } } } { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 816 -376 -200 832 "P1\[7..0\]" "" } { 1384 120 184 1400 "P1\[0\]" "" } { 864 632 720 880 "P1\[3\]" "" } { 1760 864 928 1776 "P1\[5\]" "" } { 976 840 888 992 "P1\[6\]" "" } { 1008 536 576 1024 "P1\[3\]" "" } { 1408 456 512 1424 "P1\[0\]" "" } { 1144 840 875 1160 "P1\[5\]" "" } { 1192 608 688 1208 "P1\[5\]" "" } { 976 -72 -24 992 "P1\[5\]" "" } { 1176 -104 -16 1192 "P1\[5\]" "" } { 1280 472 520 1296 "P1\[4\]" "" } { 

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