core_1c6.map.qmsg

运用TLC5510A高速(20M),扫描出波形,测量相位差,两个TLC5510A测两个波形.

{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "Din4 bus_connect.v(21) " "Warning (10235): Verilog HDL Always Construct warning at bus_connect.v(21): variable \"Din4\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 21 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "Din5 bus_connect.v(22) " "Warning (10235): Verilog HDL Always Construct warning at bus_connect.v(22): variable \"Din5\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 22 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "Din6 bus_connect.v(23) " "Warning (10235): Verilog HDL Always Construct warning at bus_connect.v(23): variable \"Din6\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 23 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "Din7 bus_connect.v(24) " "Warning (10235): Verilog HDL Always Construct warning at bus_connect.v(24): variable \"Din7\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 24 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "bus_connect.v(16) " "Warning (10270): Verilog HDL statement warning at bus_connect.v(16): incomplete Case Statement has no default case item" {  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 16 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "Data_Temp bus_connect.v(14) " "Warning (10240): Verilog HDL Always Construct warning at bus_connect.v(14): variable \"Data_Temp\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"Data_Temp\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 14 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ce_gao ce_gao:inst12 " "Info: Elaborating entity \"ce_gao\" for hierarchy \"ce_gao:inst12\"" {  } { { "core_1c6.bdf" "inst12" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 1520 112 264 1680 "inst12" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 ce_gao.v(29) " "Warning (10230): Verilog HDL assignment warning at ce_gao.v(29): truncated value with size 32 to match size of target (24)" {  } { { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 29 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "addr ce_gao.v(33) " "Warning (10235): Verilog HDL Always Construct warning at ce_gao.v(33): variable \"addr\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 33 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 ce_gao.v(34) " "Warning (10271): Verilog HDL Case Statement warning at ce_gao.v(34): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 34 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "counter ce_gao.v(34) " "Warning (10235): Verilog HDL Always Construct warning at ce_gao.v(34): variable \"counter\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 34 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 ce_gao.v(35) " "Warning (10271): Verilog HDL Case Statement warning at ce_gao.v(35): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 35 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "counter ce_gao.v(35) " "Warning (10235): Verilog HDL Always Construct warning at ce_gao.v(35): variable \"counter\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 35 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 2 ce_gao.v(36) " "Warning (10271): Verilog HDL Case Statement warning at ce_gao.v(36): size of case item expression (32) exceeds the size of the case expression (2)" {  } { { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 36 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "counter ce_gao.v(36) " "Warning (10235): Verilog HDL Always Construct warning at ce_gao.v(36): variable \"counter\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 36 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "div_1000.v 1 1 " "Warning: Using design file div_1000.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 div_1000 " "Info: Found entity 1: div_1000" {  } { { "div_1000.v" "" { Text "D:/Test_Phase/cexiang1/div_1000.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div_1000 div_1000:inst33 " "Info: Elaborating entity \"div_1000\" for hierarchy \"div_1000:inst33\"" {  } { { "core_1c6.bdf" "inst33" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 1792 -352 -224 1888 "inst33" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 div_1000.v(13) " "Warning (10230): Verilog HDL assignment warning at div_1000.v(13): truncated value with size 32 to match size of target (10)" {  } { { "div_1000.v" "" { Text "D:/Test_Phase/cexiang1/div_1000.v" 13 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_PREVIOUSLY_DECLARED_WITHOUT_RANGE" "data_out CONTER8.v(4) " "Warning (10226): Verilog HDL Multiple Declaration warning at CONTER8.v(4): net, port, or variable \"data_out\" was previously declared without a range" {  } { { "CONTER8.v" "" { Text "D:/Test_Phase/cexiang1/CONTER8.v" 4 0 0 } }  } 0 10226 "Verilog HDL Multiple Declaration warning at %2!s!: net, port, or variable \"%1!s!\" was previously declared without a range" 0 0}
{ "Info" "IVRFX_GENERIC_INFO_WITH_LOC" "data_out is declared here CONTER8.v(3) " "Info (10007): Verilog HDL or VHDL information at CONTER8.v(3): data_out is declared here" {  } { { "CONTER8.v" "" { Text "D:/Test_Phase/cexiang1/CONTER8.v" 3 0 0 } }  } 0 10007 "Verilog HDL or VHDL information at %2!s!: %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "CONTER8.v 1 1 " "Warning: Using design file CONTER8.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 CONTER8 " "Info: Found entity 1: CONTER8" {  } { { "CONTER8.v" "" { Text "D:/Test_Phase/cexiang1/CONTER8.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CONTER8 CONTER8:inst35 " "Info: Elaborating entity \"CONTER8\" for hierarchy \"CONTER8:inst35\"" {  } { { "core_1c6.bdf" "inst35" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 1808 -112 40 1904 "inst35" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 CONTER8.v(11) " "Warning (10230): Verilog HDL assignment warning at CONTER8.v(11): truncated value with size 32 to match size of target (10)" {  } { { "CONTER8.v" "" { Text "D:/Test_Phase/cexiang1/CONTER8.v" 11 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add18:inst47\|DATA\[17\] data_in GND " "Warning: Reduced register \"add18:inst47\|DATA\[17\]\" with stuck data_in port to stuck value GND" {  } { { "add18.v" "" { Text "D:/Test_Phase/cexiang1/add18.v" 20 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add18:inst47\|DATA\[16\] data_in GND " "Warning: Reduced register \"add18:inst47\|DATA\[16\]\" with stuck data_in port to stuck value GND" {  } { { "add18.v" "" { Text "D:/Test_Phase/cexiang1/add18.v" 20 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}