core_1c6.map.qmsg

运用TLC5510A高速(20M),扫描出波形,测量相位差,两个TLC5510A测两个波形.

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 scankey.v(24) " "Warning (10230): Verilog HDL assignment warning at scankey.v(24): truncated value with size 32 to match size of target (1)" {  } { { "scankey.v" "" { Text "D:/Test_Phase/cexiang1/scankey.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 scankey.v(42) " "Warning (10230): Verilog HDL assignment warning at scankey.v(42): truncated value with size 32 to match size of target (3)" {  } { { "scankey.v" "" { Text "D:/Test_Phase/cexiang1/scankey.v" 42 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "chufa chufa:inst21 " "Info: Elaborating entity \"chufa\" for hierarchy \"chufa:inst21\"" {  } { { "core_1c6.bdf" "inst21" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 1248 520 616 1344 "inst21" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Tlc5510 Tlc5510:inst20 " "Info: Elaborating entity \"Tlc5510\" for hierarchy \"Tlc5510:inst20\"" {  } { { "core_1c6.bdf" "inst20" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 1368 184 352 1464 "inst20" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add18 add18:inst47 " "Info: Elaborating entity \"add18\" for hierarchy \"add18:inst47\"" {  } { { "core_1c6.bdf" "inst47" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 1112 688 840 1272 "inst47" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "11 10 add18.v(12) " "Warning (10230): Verilog HDL assignment warning at add18.v(12): truncated value with size 11 to match size of target (10)" {  } { { "add18.v" "" { Text "D:/Test_Phase/cexiang1/add18.v" 12 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fp_2 fp_2:inst18 " "Info: Elaborating entity \"fp_2\" for hierarchy \"fp_2:inst18\"" {  } { { "core_1c6.bdf" "inst18" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 1224 -384 -288 1320 "inst18" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 fp_2.v(12) " "Warning (10230): Verilog HDL assignment warning at fp_2.v(12): truncated value with size 32 to match size of target (1)" {  } { { "fp_2.v" "" { Text "D:/Test_Phase/cexiang1/fp_2.v" 12 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_ctl data_ctl:inst10 " "Info: Elaborating entity \"data_ctl\" for hierarchy \"data_ctl:inst10\"" {  } { { "core_1c6.bdf" "inst10" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 136 232 392 232 "inst10" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "select2_1 select2_1:inst31 " "Info: Elaborating entity \"select2_1\" for hierarchy \"select2_1:inst31\"" {  } { { "core_1c6.bdf" "inst31" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 928 888 1032 1024 "inst31" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "select_q.v 1 1 " "Warning: Using design file select_q.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 select_q " "Info: Found entity 1: select_q" {  } { { "select_q.v" "" { Text "D:/Test_Phase/cexiang1/select_q.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "select_q select_q:inst19 " "Info: Elaborating entity \"select_q\" for hierarchy \"select_q:inst19\"" {  } { { "core_1c6.bdf" "inst19" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 816 720 864 944 "inst19" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "RAM_1K.v 1 1 " "Warning: Using design file RAM_1K.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 RAM_1K " "Info: Found entity 1: RAM_1K" {  } { { "RAM_1K.v" "" { Text "D:/Test_Phase/cexiang1/RAM_1K.v" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RAM_1K RAM_1K:inst5 " "Info: Elaborating entity \"RAM_1K\" for hierarchy \"RAM_1K:inst5\"" {  } { { "core_1c6.bdf" "inst5" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 920 208 464 1096 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram RAM_1K:inst5\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"RAM_1K:inst5\|altsyncram:altsyncram_component\"" {  } { { "RAM_1K.v" "altsyncram_component" { Text "D:/Test_Phase/cexiang1/RAM_1K.v" 64 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_aqb1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_aqb1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_aqb1 " "Info: Found entity 1: altsyncram_aqb1" {  } { { "db/altsyncram_aqb1.tdf" "" { Text "D:/Test_Phase/cexiang1/db/altsyncram_aqb1.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_aqb1 RAM_1K:inst5\|altsyncram:altsyncram_component\|altsyncram_aqb1:auto_generated " "Info: Elaborating entity \"altsyncram_aqb1\" for hierarchy \"RAM_1K:inst5\|altsyncram:altsyncram_component\|altsyncram_aqb1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RAM_ADDR RAM_ADDR:inst13 " "Info: Elaborating entity \"RAM_ADDR\" for hierarchy \"RAM_ADDR:inst13\"" {  } { { "core_1c6.bdf" "inst13" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 648 392 544 744 "inst13" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ASIC74573 ASIC74573:inst " "Info: Elaborating entity \"ASIC74573\" for hierarchy \"ASIC74573:inst\"" {  } { { "core_1c6.bdf" "inst" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 240 256 400 336 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "BUS_Connect BUS_Connect:inst9 " "Info: Elaborating entity \"BUS_Connect\" for hierarchy \"BUS_Connect:inst9\"" {  } { { "core_1c6.bdf" "inst9" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 488 160 312 808 "inst9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "Din0 bus_connect.v(17) " "Warning (10235): Verilog HDL Always Construct warning at bus_connect.v(17): variable \"Din0\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 17 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "Din1 bus_connect.v(18) " "Warning (10235): Verilog HDL Always Construct warning at bus_connect.v(18): variable \"Din1\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 18 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "Din2 bus_connect.v(19) " "Warning (10235): Verilog HDL Always Construct warning at bus_connect.v(19): variable \"Din2\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 19 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "Din3 bus_connect.v(20) " "Warning (10235): Verilog HDL Always Construct warning at bus_connect.v(20): variable \"Din3\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 20 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}