core_1c6.map.qmsg

运用TLC5510A高速(20M),扫描出波形,测量相位差,两个TLC5510A测两个波形.

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ce_gao.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ce_gao.v" { { "Info" "ISGN_ENTITY_NAME" "1 ce_gao " "Info: Found entity 1: ce_gao" {  } { { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "core_1c6 " "Info: Elaborating entity \"core_1c6\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "OR2 inst30 " "Warning: Block or symbol \"OR2\" of instance \"inst30\" overlaps another block or symbol" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 1160 -16 48 1208 "inst30" "" } } } }  } 0 0 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "OR2 inst37 " "Warning: Block or symbol \"OR2\" of instance \"inst37\" overlaps another block or symbol" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 960 -24 40 1008 "inst37" "" } } } }  } 0 0 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "Din2 BUS_Connect inst9 " "Warning: Port \"Din2\" of type BUS_Connect and instance \"inst9\" is missing source signal" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 488 160 312 808 "inst9" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "Din5 BUS_Connect inst9 " "Warning: Port \"Din5\" of type BUS_Connect and instance \"inst9\" is missing source signal" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 488 160 312 808 "inst9" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "Din7 BUS_Connect inst9 " "Warning: Port \"Din7\" of type BUS_Connect and instance \"inst9\" is missing source signal" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 488 160 312 808 "inst9" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Adr4_16 Adr4_16:inst45 " "Info: Elaborating entity \"Adr4_16\" for hierarchy \"Adr4_16:inst45\"" {  } { { "core_1c6.bdf" "inst45" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 360 248 408 456 "inst45" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Adr4_16.v(14) " "Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(14): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Adr4_16.v" "" { Text "D:/Test_Phase/cexiang1/Adr4_16.v" 14 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Adr4_16.v(15) " "Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(15): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Adr4_16.v" "" { Text "D:/Test_Phase/cexiang1/Adr4_16.v" 15 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Adr4_16.v(16) " "Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(16): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Adr4_16.v" "" { Text "D:/Test_Phase/cexiang1/Adr4_16.v" 16 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Adr4_16.v(17) " "Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(17): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Adr4_16.v" "" { Text "D:/Test_Phase/cexiang1/Adr4_16.v" 17 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Adr4_16.v(18) " "Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(18): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Adr4_16.v" "" { Text "D:/Test_Phase/cexiang1/Adr4_16.v" 18 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Adr4_16.v(19) " "Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(19): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Adr4_16.v" "" { Text "D:/Test_Phase/cexiang1/Adr4_16.v" 19 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Adr4_16.v(20) " "Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(20): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Adr4_16.v" "" { Text "D:/Test_Phase/cexiang1/Adr4_16.v" 20 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Adr4_16.v(21) " "Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(21): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Adr4_16.v" "" { Text "D:/Test_Phase/cexiang1/Adr4_16.v" 21 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Adr4_16.v(22) " "Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(22): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Adr4_16.v" "" { Text "D:/Test_Phase/cexiang1/Adr4_16.v" 22 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Adr4_16.v(23) " "Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(23): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Adr4_16.v" "" { Text "D:/Test_Phase/cexiang1/Adr4_16.v" 23 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Adr4_16.v(24) " "Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(24): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Adr4_16.v" "" { Text "D:/Test_Phase/cexiang1/Adr4_16.v" 24 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Adr4_16.v(25) " "Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(25): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Adr4_16.v" "" { Text "D:/Test_Phase/cexiang1/Adr4_16.v" 25 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Adr4_16.v(26) " "Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(26): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Adr4_16.v" "" { Text "D:/Test_Phase/cexiang1/Adr4_16.v" 26 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Adr4_16.v(27) " "Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(27): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Adr4_16.v" "" { Text "D:/Test_Phase/cexiang1/Adr4_16.v" 27 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Adr4_16.v(28) " "Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(28): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Adr4_16.v" "" { Text "D:/Test_Phase/cexiang1/Adr4_16.v" 28 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 4 Adr4_16.v(29) " "Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(29): size of case item expression (32) exceeds the size of the case expression (4)" {  } { { "Adr4_16.v" "" { Text "D:/Test_Phase/cexiang1/Adr4_16.v" 29 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ScanKey ScanKey:inst15 " "Info: Elaborating entity \"ScanKey\" for hierarchy \"ScanKey:inst15\"" {  } { { "core_1c6.bdf" "inst15" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 0 248 392 128 "inst15" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}