scankey.v

运用TLC5510A高速(20M),扫描出波形,测量相位差,两个TLC5510A测两个波形.

module ScanKey(CS,RD,CLK,Dout,KC,KR,KP,INT);

input CLK;       //Clock signal of the module
input CS;
input RD;
inout [2:0] KC;  //Columns of 4X4 KeyBoard
inout [5:0] KR;  //Rows of 4X4 KeyBoard
input [5:0] KP;  //6 Gpro key
output [7:0] Dout;  //Output the numeber of the key 
output INT;      //Interrupt signal 

reg[2:0] KC_temp;
reg[5:0] KR_temp;

reg[2:0] KC_out;
reg[5:0] KR_out; 

reg[7:0] Key_temp;
 
reg[2:0] Count;  //Couter for scanning keyboard

assign KC=(Count==0)? 3'bzzz:KC_out;
assign KR=(Count==3)? 6'bzzzzzz:KR_out;
assign INT=(Key_temp[4:0]==31)? 1:0;            //Generate Interrupt Signal
assign Dout=((!CS)&(!RD))? Key_temp : 8'hzz;

always @(KP)
  begin
    case(KP)
     6'b111110:Key_temp[7:5]<=1;
     6'b111101:Key_temp[7:5]<=2;
     6'b111011:Key_temp[7:5]<=3;
     6'b110111:Key_temp[7:5]<=4;
     6'b101111:Key_temp[7:5]<=5;
     6'b011111:Key_temp[7:5]<=6;
     default:Key_temp[7:5]<=0;
    endcase
  end

always@(posedge CLK)
  begin
    Count<=Count+1;
  end

always@(posedge CLK)
  begin
    if(Count==6)
       begin
         KC_out<=3'b111;
         KR_out<=6'b000000;
       end
    if(Count==0)
         KC_temp<=KC;
    if(Count==1)
       begin
         KC_out<=3'b000;
         KR_out<=6'b111111;
       end
    if(Count==3)
         KR_temp<=KR;
  end  

always@(posedge CLK)
  begin
    case({KC_temp,KR_temp})
      9'b110111110:Key_temp[4:0]<=0;
      9'b110111101:Key_temp[4:0]<=1;
      9'b110111011:Key_temp[4:0]<=2;
      9'b110110111:Key_temp[4:0]<=3;
      9'b110101111:Key_temp[4:0]<=4;
      9'b110011111:Key_temp[4:0]<=5;
      9'b101111110:Key_temp[4:0]<=6;
      9'b101111101:Key_temp[4:0]<=7;
      9'b101111011:Key_temp[4:0]<=8;
      9'b101110111:Key_temp[4:0]<=9;
      9'b101101111:Key_temp[4:0]<=10;
      9'b101011111:Key_temp[4:0]<=11;
      9'b011111110:Key_temp[4:0]<=12;
      9'b011111101:Key_temp[4:0]<=13;
      9'b011111011:Key_temp[4:0]<=14;
      9'b011110111:Key_temp[4:0]<=15;
      9'b011101111:Key_temp[4:0]<=16;
      9'b011011111:Key_temp[4:0]<=17;
     default:Key_temp[4:0]<=31;
    endcase
  end
endmodule