⭐ 欢迎来到虫虫下载站！ | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站
📤 上传资源

📄 core_1c6.fit.eqn

📁 运用TLC5510A高速(20M),扫描出波形,测量相位差,两个TLC5510A测两个波形.
💻 EQN
📖 第 1 页 / 共 5 页
字号:
🔍
12345 
U1_q_b[6]_PORT_B_read_enable = inst38;
U1_q_b[6]_PORT_B_read_enable_reg = DFFE(U1_q_b[6]_PORT_B_read_enable, U1_q_b[6]_clock_1, , , );
U1_q_b[6]_clock_0 = GLOBAL(CLK_40);
U1_q_b[6]_clock_1 = GLOBAL(CLK_40);
U1_q_b[6]_clock_enable_0 = inst37;
U1_q_b[6]_PORT_B_data_out = MEMORY(U1_q_b[6]_PORT_A_data_in_reg, , U1_q_b[6]_PORT_A_address_reg, U1_q_b[6]_PORT_B_address_reg, U1_q_b[6]_PORT_A_write_enable_reg, U1_q_b[6]_PORT_B_read_enable_reg, , , U1_q_b[6]_clock_0, U1_q_b[6]_clock_1, U1_q_b[6]_clock_enable_0, , , );
U1_q_b[6]_PORT_B_data_out_reg = DFFE(U1_q_b[6]_PORT_B_data_out, U1_q_b[6]_clock_1, , , );
U1_q_b[1] = U1_q_b[6]_PORT_B_data_out_reg[3];

--U1_q_b[2] is RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[2] at M4K_X17_Y15
U1_q_b[6]_PORT_A_data_in = BUS(in1[6], in1[5], in1[2], in1[1]);
U1_q_b[6]_PORT_A_data_in_reg = DFFE(U1_q_b[6]_PORT_A_data_in, U1_q_b[6]_clock_0, , , U1_q_b[6]_clock_enable_0);
U1_q_b[6]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U1_q_b[6]_PORT_A_address_reg = DFFE(U1_q_b[6]_PORT_A_address, U1_q_b[6]_clock_0, , , U1_q_b[6]_clock_enable_0);
U1_q_b[6]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U1_q_b[6]_PORT_B_address_reg = DFFE(U1_q_b[6]_PORT_B_address, U1_q_b[6]_clock_1, , , );
U1_q_b[6]_PORT_A_write_enable = VCC;
U1_q_b[6]_PORT_A_write_enable_reg = DFFE(U1_q_b[6]_PORT_A_write_enable, U1_q_b[6]_clock_0, , , U1_q_b[6]_clock_enable_0);
U1_q_b[6]_PORT_B_read_enable = inst38;
U1_q_b[6]_PORT_B_read_enable_reg = DFFE(U1_q_b[6]_PORT_B_read_enable, U1_q_b[6]_clock_1, , , );
U1_q_b[6]_clock_0 = GLOBAL(CLK_40);
U1_q_b[6]_clock_1 = GLOBAL(CLK_40);
U1_q_b[6]_clock_enable_0 = inst37;
U1_q_b[6]_PORT_B_data_out = MEMORY(U1_q_b[6]_PORT_A_data_in_reg, , U1_q_b[6]_PORT_A_address_reg, U1_q_b[6]_PORT_B_address_reg, U1_q_b[6]_PORT_A_write_enable_reg, U1_q_b[6]_PORT_B_read_enable_reg, , , U1_q_b[6]_clock_0, U1_q_b[6]_clock_1, U1_q_b[6]_clock_enable_0, , , );
U1_q_b[6]_PORT_B_data_out_reg = DFFE(U1_q_b[6]_PORT_B_data_out, U1_q_b[6]_clock_1, , , );
U1_q_b[2] = U1_q_b[6]_PORT_B_data_out_reg[2];

--U1_q_b[5] is RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[5] at M4K_X17_Y15
U1_q_b[6]_PORT_A_data_in = BUS(in1[6], in1[5], in1[2], in1[1]);
U1_q_b[6]_PORT_A_data_in_reg = DFFE(U1_q_b[6]_PORT_A_data_in, U1_q_b[6]_clock_0, , , U1_q_b[6]_clock_enable_0);
U1_q_b[6]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U1_q_b[6]_PORT_A_address_reg = DFFE(U1_q_b[6]_PORT_A_address, U1_q_b[6]_clock_0, , , U1_q_b[6]_clock_enable_0);
U1_q_b[6]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U1_q_b[6]_PORT_B_address_reg = DFFE(U1_q_b[6]_PORT_B_address, U1_q_b[6]_clock_1, , , );
U1_q_b[6]_PORT_A_write_enable = VCC;
U1_q_b[6]_PORT_A_write_enable_reg = DFFE(U1_q_b[6]_PORT_A_write_enable, U1_q_b[6]_clock_0, , , U1_q_b[6]_clock_enable_0);
U1_q_b[6]_PORT_B_read_enable = inst38;
U1_q_b[6]_PORT_B_read_enable_reg = DFFE(U1_q_b[6]_PORT_B_read_enable, U1_q_b[6]_clock_1, , , );
U1_q_b[6]_clock_0 = GLOBAL(CLK_40);
U1_q_b[6]_clock_1 = GLOBAL(CLK_40);
U1_q_b[6]_clock_enable_0 = inst37;
U1_q_b[6]_PORT_B_data_out = MEMORY(U1_q_b[6]_PORT_A_data_in_reg, , U1_q_b[6]_PORT_A_address_reg, U1_q_b[6]_PORT_B_address_reg, U1_q_b[6]_PORT_A_write_enable_reg, U1_q_b[6]_PORT_B_read_enable_reg, , , U1_q_b[6]_clock_0, U1_q_b[6]_clock_1, U1_q_b[6]_clock_enable_0, , , );
U1_q_b[6]_PORT_B_data_out_reg = DFFE(U1_q_b[6]_PORT_B_data_out, U1_q_b[6]_clock_1, , , );
U1_q_b[5] = U1_q_b[6]_PORT_B_data_out_reg[1];


--D1L13 is select2_1:inst31|out_q[6]~986 at LC_X16_Y13_N9
--operation mode is normal

D1L13 = A1L130 & (U2_q_b[6]) # !A1L130 & U1_q_b[6];


--L1_out_q[6] is select_q:inst19|out_q[6] at LC_X16_Y13_N3
--operation mode is normal

L1_out_q[6]_lut_out = A1L130 & (in2[6]) # !A1L130 & in1[6];
L1_out_q[6] = DFFEAS(L1_out_q[6]_lut_out, GLOBAL(K3_Cout), VCC, , , , , , );


--D1L14 is select2_1:inst31|out_q[6]~987 at LC_X16_Y13_N6
--operation mode is normal

D1L14 = A1L128 & (D1L13) # !A1L128 & L1_out_q[6];


--U2_q_b[5] is RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[5] at M4K_X17_Y14
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
U2_q_b[5]_PORT_A_data_in = BUS(in2[5], in2[3], in2[1], in2[0]);
U2_q_b[5]_PORT_A_data_in_reg = DFFE(U2_q_b[5]_PORT_A_data_in, U2_q_b[5]_clock_0, , , U2_q_b[5]_clock_enable_0);
U2_q_b[5]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U2_q_b[5]_PORT_A_address_reg = DFFE(U2_q_b[5]_PORT_A_address, U2_q_b[5]_clock_0, , , U2_q_b[5]_clock_enable_0);
U2_q_b[5]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U2_q_b[5]_PORT_B_address_reg = DFFE(U2_q_b[5]_PORT_B_address, U2_q_b[5]_clock_1, , , );
U2_q_b[5]_PORT_A_write_enable = VCC;
U2_q_b[5]_PORT_A_write_enable_reg = DFFE(U2_q_b[5]_PORT_A_write_enable, U2_q_b[5]_clock_0, , , U2_q_b[5]_clock_enable_0);
U2_q_b[5]_PORT_B_read_enable = inst36;
U2_q_b[5]_PORT_B_read_enable_reg = DFFE(U2_q_b[5]_PORT_B_read_enable, U2_q_b[5]_clock_1, , , );
U2_q_b[5]_clock_0 = GLOBAL(CLK_40);
U2_q_b[5]_clock_1 = GLOBAL(CLK_40);
U2_q_b[5]_clock_enable_0 = inst37;
U2_q_b[5]_PORT_B_data_out = MEMORY(U2_q_b[5]_PORT_A_data_in_reg, , U2_q_b[5]_PORT_A_address_reg, U2_q_b[5]_PORT_B_address_reg, U2_q_b[5]_PORT_A_write_enable_reg, U2_q_b[5]_PORT_B_read_enable_reg, , , U2_q_b[5]_clock_0, U2_q_b[5]_clock_1, U2_q_b[5]_clock_enable_0, , , );
U2_q_b[5]_PORT_B_data_out_reg = DFFE(U2_q_b[5]_PORT_B_data_out, U2_q_b[5]_clock_1, , , );
U2_q_b[5] = U2_q_b[5]_PORT_B_data_out_reg[0];

--U2_q_b[0] is RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[0] at M4K_X17_Y14
U2_q_b[5]_PORT_A_data_in = BUS(in2[5], in2[3], in2[1], in2[0]);
U2_q_b[5]_PORT_A_data_in_reg = DFFE(U2_q_b[5]_PORT_A_data_in, U2_q_b[5]_clock_0, , , U2_q_b[5]_clock_enable_0);
U2_q_b[5]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U2_q_b[5]_PORT_A_address_reg = DFFE(U2_q_b[5]_PORT_A_address, U2_q_b[5]_clock_0, , , U2_q_b[5]_clock_enable_0);
U2_q_b[5]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U2_q_b[5]_PORT_B_address_reg = DFFE(U2_q_b[5]_PORT_B_address, U2_q_b[5]_clock_1, , , );
U2_q_b[5]_PORT_A_write_enable = VCC;
U2_q_b[5]_PORT_A_write_enable_reg = DFFE(U2_q_b[5]_PORT_A_write_enable, U2_q_b[5]_clock_0, , , U2_q_b[5]_clock_enable_0);
U2_q_b[5]_PORT_B_read_enable = inst36;
U2_q_b[5]_PORT_B_read_enable_reg = DFFE(U2_q_b[5]_PORT_B_read_enable, U2_q_b[5]_clock_1, , , );
U2_q_b[5]_clock_0 = GLOBAL(CLK_40);
U2_q_b[5]_clock_1 = GLOBAL(CLK_40);
U2_q_b[5]_clock_enable_0 = inst37;
U2_q_b[5]_PORT_B_data_out = MEMORY(U2_q_b[5]_PORT_A_data_in_reg, , U2_q_b[5]_PORT_A_address_reg, U2_q_b[5]_PORT_B_address_reg, U2_q_b[5]_PORT_A_write_enable_reg, U2_q_b[5]_PORT_B_read_enable_reg, , , U2_q_b[5]_clock_0, U2_q_b[5]_clock_1, U2_q_b[5]_clock_enable_0, , , );
U2_q_b[5]_PORT_B_data_out_reg = DFFE(U2_q_b[5]_PORT_B_data_out, U2_q_b[5]_clock_1, , , );
U2_q_b[0] = U2_q_b[5]_PORT_B_data_out_reg[3];

--U2_q_b[1] is RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[1] at M4K_X17_Y14
U2_q_b[5]_PORT_A_data_in = BUS(in2[5], in2[3], in2[1], in2[0]);
U2_q_b[5]_PORT_A_data_in_reg = DFFE(U2_q_b[5]_PORT_A_data_in, U2_q_b[5]_clock_0, , , U2_q_b[5]_clock_enable_0);
U2_q_b[5]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U2_q_b[5]_PORT_A_address_reg = DFFE(U2_q_b[5]_PORT_A_address, U2_q_b[5]_clock_0, , , U2_q_b[5]_clock_enable_0);
U2_q_b[5]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U2_q_b[5]_PORT_B_address_reg = DFFE(U2_q_b[5]_PORT_B_address, U2_q_b[5]_clock_1, , , );
U2_q_b[5]_PORT_A_write_enable = VCC;
U2_q_b[5]_PORT_A_write_enable_reg = DFFE(U2_q_b[5]_PORT_A_write_enable, U2_q_b[5]_clock_0, , , U2_q_b[5]_clock_enable_0);
U2_q_b[5]_PORT_B_read_enable = inst36;
U2_q_b[5]_PORT_B_read_enable_reg = DFFE(U2_q_b[5]_PORT_B_read_enable, U2_q_b[5]_clock_1, , , );
U2_q_b[5]_clock_0 = GLOBAL(CLK_40);
U2_q_b[5]_clock_1 = GLOBAL(CLK_40);
U2_q_b[5]_clock_enable_0 = inst37;
U2_q_b[5]_PORT_B_data_out = MEMORY(U2_q_b[5]_PORT_A_data_in_reg, , U2_q_b[5]_PORT_A_address_reg, U2_q_b[5]_PORT_B_address_reg, U2_q_b[5]_PORT_A_write_enable_reg, U2_q_b[5]_PORT_B_read_enable_reg, , , U2_q_b[5]_clock_0, U2_q_b[5]_clock_1, U2_q_b[5]_clock_enable_0, , , );
U2_q_b[5]_PORT_B_data_out_reg = DFFE(U2_q_b[5]_PORT_B_data_out, U2_q_b[5]_clock_1, , , );
U2_q_b[1] = U2_q_b[5]_PORT_B_data_out_reg[2];

--U2_q_b[3] is RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[3] at M4K_X17_Y14
U2_q_b[5]_PORT_A_data_in = BUS(in2[5], in2[3], in2[1], in2[0]);
U2_q_b[5]_PORT_A_data_in_reg = DFFE(U2_q_b[5]_PORT_A_data_in, U2_q_b[5]_clock_0, , , U2_q_b[5]_clock_enable_0);
U2_q_b[5]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U2_q_b[5]_PORT_A_address_reg = DFFE(U2_q_b[5]_PORT_A_address, U2_q_b[5]_clock_0, , , U2_q_b[5]_clock_enable_0);
U2_q_b[5]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U2_q_b[5]_PORT_B_address_reg = DFFE(U2_q_b[5]_PORT_B_address, U2_q_b[5]_clock_1, , , );
U2_q_b[5]_PORT_A_write_enable = VCC;
U2_q_b[5]_PORT_A_write_enable_reg = DFFE(U2_q_b[5]_PORT_A_write_enable, U2_q_b[5]_clock_0, , , U2_q_b[5]_clock_enable_0);
U2_q_b[5]_PORT_B_read_enable = inst36;
U2_q_b[5]_PORT_B_read_enable_reg = DFFE(U2_q_b[5]_PORT_B_read_enable, U2_q_b[5]_clock_1, , , );
U2_q_b[5]_clock_0 = GLOBAL(CLK_40);
U2_q_b[5]_clock_1 = GLOBAL(CLK_40);
U2_q_b[5]_clock_enable_0 = inst37;
U2_q_b[5]_PORT_B_data_out = MEMORY(U2_q_b[5]_PORT_A_data_in_reg, , U2_q_b[5]_PORT_A_address_reg, U2_q_b[5]_PORT_B_address_reg, U2_q_b[5]_PORT_A_write_enable_reg, U2_q_b[5]_PORT_B_read_enable_reg, , , U2_q_b[5]_clock_0, U2_q_b[5]_clock_1, U2_q_b[5]_clock_enable_0, , , );
U2_q_b[5]_PORT_B_data_out_reg = DFFE(U2_q_b[5]_PORT_B_data_out, U2_q_b[5]_clock_1, , , );
U2_q_b[3] = U2_q_b[5]_PORT_B_data_out_reg[1];


--D1L11 is select2_1:inst31|out_q[5]~988 at LC_X15_Y11_N4
--operation mode is normal

D1L11 = A1L130 & U2_q_b[5] # !A1L130 & (U1_q_b[5]);


--L1_out_q[5] is select_q:inst19|out_q[5] at LC_X15_Y11_N5
--operation mode is normal

L1_out_q[5]_lut_out = A1L130 & (in2[5]) # !A1L130 & in1[5];
L1_out_q[5] = DFFEAS(L1_out_q[5]_lut_out, GLOBAL(K3_Cout), VCC, , , , , , );


--D1L12 is select2_1:inst31|out_q[5]~989 at LC_X15_Y11_N8
--operation mode is normal

D1L12 = A1L128 & (D1L11) # !A1L128 & L1_out_q[5];


--D1L9 is select2_1:inst31|out_q[4]~990 at LC_X16_Y12_N5
--operation mode is normal

D1L9 = A1L130 & (U2_q_b[4]) # !A1L130 & U1_q_b[4];


--L1_out_q[4] is select_q:inst19|out_q[4] at LC_X16_Y12_N6
--operation mode is normal

L1_out_q[4]_lut_out = A1L130 & in2[4] # !A1L130 & (in1[4]);
L1_out_q[4] = DFFEAS(L1_out_q[4]_lut_out, GLOBAL(K3_Cout), VCC, , , , , , );


--D1L10 is select2_1:inst31|out_q[4]~991 at LC_X16_Y12_N8
--operation mode is normal

D1L10 = A1L128 & D1L9 # !A1L128 & (L1_out_q[4]);


--D1L7 is select2_1:inst31|out_q[3]~992 at LC_X15_Y11_N6
--operation mode is normal

D1L7 = A1L130 & (U2_q_b[3]) # !A1L130 & (U1_q_b[3]);


--L1_out_q[3] is select_q:inst19|out_q[3] at LC_X15_Y11_N1
--operation mode is normal

L1_out_q[3]_lut_out = A1L130 & (in2[3]) # !A1L130 & in1[3];
L1_out_q[3] = DFFEAS(L1_out_q[3]_lut_out, GLOBAL(K3_Cout), VCC, , , , , , );


--D1L8 is select2_1:inst31|out_q[3]~993 at LC_X15_Y11_N2
--operation mode is normal

D1L8 = A1L128 & D1L7 # !A1L128 & (L1_out_q[3]);


--D1L5 is select2_1:inst31|out_q[2]~994 at LC_X16_Y14_N3
--operation mode is normal

D1L5 = A1L130 & (U2_q_b[2]) # !A1L130 & U1_q_b[2];


--L1_out_q[2] is select_q:inst19|out_q[2] at LC_X16_Y14_N8
--operation mode is normal

L1_out_q[2]_lut_out = A1L130 & (in2[2]) # !A1L130 & (in1[2]);
L1_out_q[2] = DFFEAS(L1_out_q[2]_lut_out, GLOBAL(K3_Cout), VCC, , , , , , );


--D1L6 is select2_1:inst31|out_q[2]~995 at LC_X16_Y14_N7
--operation mode is normal

D1L6 = A1L128 & D1L5 # !A1L128 & (L1_out_q[2]);


--D1L3 is select2_1:inst31|out_q[1]~996 at LC_X15_Y11_N7
--operation mode is normal

D1L3 = A1L130 & (U2_q_b[1]) # !A1L130 & (U1_q_b[1]);


--L1_out_q[1] is select_q:inst19|out_q[1] at LC_X15_Y11_N3
--operation mode is normal

L1_out_q[1]_lut_out = A1L130 & (in2[1]) # !A1L130 & in1[1];
L1_out_q[1] = DFFEAS(L1_out_q[1]_lut_out, GLOBAL(K3_Cout), VCC, , , , , , );


--D1L4 is select2_1:inst31|out_q[1]~997 at LC_X15_Y11_N9
--operation mode is normal

D1L4 = A1L128 & (D1L3) # !A1L128 & L1_out_q[1];


--D1L1 is select2_1:inst31|out_q[0]~998 at LC_X15_Y14_N7
--operation mode is normal

D1L1 = A1L130 & (U2_q_b[0]) # !A1L130 & U1_q_b[0];


--L1_out_q[0] is select_q:inst19|out_q[0] at LC_X15_Y14_N8
--operation mode is normal

L1_out_q[0]_lut_out = A1L130 & in2[0] # !A1L130 & (in1[0]);
L1_out_q[0] = DFFEAS(L1_out_q[0]_lut_out, GLOBAL(K3_Cout), VCC, , , , , , );


--D1L2 is select2_1:inst31|out_q[0]~999 at LC_X15_Y14_N6
--operation mode is normal

D1L2 = A1L128 & (D1L1) # !A1L128 & L1_out_q[0];


--J1_KR_temp[0] is ScanKey:inst15|KR_temp[0] at LC_X28_Y1_N8
--operation mode is normal

J1_KR_temp[0]_lut_out = A1L55;
J1_KR_temp[0] = DFFEAS(J1_KR_temp[0]_lut_out, GLOBAL(ALE), VCC, , !A1L143, , , , );


--J1_KR_temp[1] is ScanKey:inst15|KR_temp[1] at LC_X28_Y1_N2
--operation mode is normal

J1_KR_temp[1]_lut_out = A1L54;
J1_KR_temp[1] = DFFEAS(J1_KR_temp[1]_lut_out, GLOBAL(ALE), VCC, , !A1L143, , , , );


--J1_KR_temp[2] is ScanKey:inst15|KR_temp[2] at LC_X28_Y1_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_KR_temp[2]_lut_out = GND;
J1_KR_temp[2] = DFFEAS(J1_KR_temp[2]_lut_out, GLOBAL(ALE), VCC, , !A1L143, A1L53, , , VCC);


--J1_KR_temp[3] is ScanKey:inst15|KR_temp[3] at LC_X28_Y1_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_KR_temp[3]_lut_out = GND;
J1_KR_temp[3] = DFFEAS(J1_KR_temp[3]_lut_out, GLOBAL(ALE), VCC, , !A1L143, A1L52, , , VCC);


--J1_KR_temp[4] is ScanKey:inst15|KR_temp[4] at LC_X28_Y1_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

J1_KR_temp[4]_lut_out = GND;
J1_KR_temp[4] = DFFEAS(J1_KR_temp[4]_lut_out, GLOBAL(ALE), VCC, , !A1L143, A1L51, , , VCC);


--J1_KR_temp[5] is ScanKey:inst15|KR_temp[5] at LC_X29_Y1_N2
--operation mode is normal

J1_KR_temp[5]_lut_out = A1L50;
J1_KR_temp[5] = DFFEAS(J1_KR_temp[5]_lut_out, GLOBAL(ALE), VCC, , !A1L143, , , , );


--J1_KC_temp[0] is ScanKey:inst15|KC_temp[0] at LC_X27_Y1_N2
12345

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -