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📄 core_1c6.fit.eqn

📁 运用TLC5510A高速(20M),扫描出波形,测量相位差,两个TLC5510A测两个波形.
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--E1L11 is BUS_Connect:inst9|Select~459 at LC_X19_Y14_N3
--operation mode is normal

E1L11 = P2[3] & P2[4] & !P2[6];


--R1L1 is Adr4_16:inst45|CSout[3]~67 at LC_X21_Y14_N6
--operation mode is normal

R1L1 = P2[5] # !E1L11 # !P2[7];


--V1_q_a[4] is ScanKey:inst15|altsyncram:reduce_or_rtl_0|altsyncram_r9l:auto_generated|q_a[4] at M4K_X17_Y1
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 5
--Port A Logical Depth: 512, Port A Logical Width: 5
--Port A Input: Registered, Port A Output: Un-registered
V1_q_a[4]_PORT_A_address = BUS(J1_KR_temp[0], J1_KR_temp[1], J1_KR_temp[2], J1_KR_temp[3], J1_KR_temp[4], J1_KR_temp[5], J1_KC_temp[0], J1_KC_temp[1], J1_KC_temp[2]);
V1_q_a[4]_PORT_A_address_reg = DFFE(V1_q_a[4]_PORT_A_address, V1_q_a[4]_clock_0, , , );
V1_q_a[4]_clock_0 = GLOBAL(ALE);
V1_q_a[4]_PORT_A_data_out = MEMORY(, , V1_q_a[4]_PORT_A_address_reg, , , , , , V1_q_a[4]_clock_0, , , , , );
V1_q_a[4] = V1_q_a[4]_PORT_A_data_out[0];

--V1_q_a[3] is ScanKey:inst15|altsyncram:reduce_or_rtl_0|altsyncram_r9l:auto_generated|q_a[3] at M4K_X17_Y1
V1_q_a[4]_PORT_A_address = BUS(J1_KR_temp[0], J1_KR_temp[1], J1_KR_temp[2], J1_KR_temp[3], J1_KR_temp[4], J1_KR_temp[5], J1_KC_temp[0], J1_KC_temp[1], J1_KC_temp[2]);
V1_q_a[4]_PORT_A_address_reg = DFFE(V1_q_a[4]_PORT_A_address, V1_q_a[4]_clock_0, , , );
V1_q_a[4]_clock_0 = GLOBAL(ALE);
V1_q_a[4]_PORT_A_data_out = MEMORY(, , V1_q_a[4]_PORT_A_address_reg, , , , , , V1_q_a[4]_clock_0, , , , , );
V1_q_a[3] = V1_q_a[4]_PORT_A_data_out[4];

--V1_q_a[2] is ScanKey:inst15|altsyncram:reduce_or_rtl_0|altsyncram_r9l:auto_generated|q_a[2] at M4K_X17_Y1
V1_q_a[4]_PORT_A_address = BUS(J1_KR_temp[0], J1_KR_temp[1], J1_KR_temp[2], J1_KR_temp[3], J1_KR_temp[4], J1_KR_temp[5], J1_KC_temp[0], J1_KC_temp[1], J1_KC_temp[2]);
V1_q_a[4]_PORT_A_address_reg = DFFE(V1_q_a[4]_PORT_A_address, V1_q_a[4]_clock_0, , , );
V1_q_a[4]_clock_0 = GLOBAL(ALE);
V1_q_a[4]_PORT_A_data_out = MEMORY(, , V1_q_a[4]_PORT_A_address_reg, , , , , , V1_q_a[4]_clock_0, , , , , );
V1_q_a[2] = V1_q_a[4]_PORT_A_data_out[3];

--V1_q_a[1] is ScanKey:inst15|altsyncram:reduce_or_rtl_0|altsyncram_r9l:auto_generated|q_a[1] at M4K_X17_Y1
V1_q_a[4]_PORT_A_address = BUS(J1_KR_temp[0], J1_KR_temp[1], J1_KR_temp[2], J1_KR_temp[3], J1_KR_temp[4], J1_KR_temp[5], J1_KC_temp[0], J1_KC_temp[1], J1_KC_temp[2]);
V1_q_a[4]_PORT_A_address_reg = DFFE(V1_q_a[4]_PORT_A_address, V1_q_a[4]_clock_0, , , );
V1_q_a[4]_clock_0 = GLOBAL(ALE);
V1_q_a[4]_PORT_A_data_out = MEMORY(, , V1_q_a[4]_PORT_A_address_reg, , , , , , V1_q_a[4]_clock_0, , , , , );
V1_q_a[1] = V1_q_a[4]_PORT_A_data_out[2];

--V1_q_a[0] is ScanKey:inst15|altsyncram:reduce_or_rtl_0|altsyncram_r9l:auto_generated|q_a[0] at M4K_X17_Y1
V1_q_a[4]_PORT_A_address = BUS(J1_KR_temp[0], J1_KR_temp[1], J1_KR_temp[2], J1_KR_temp[3], J1_KR_temp[4], J1_KR_temp[5], J1_KC_temp[0], J1_KC_temp[1], J1_KC_temp[2]);
V1_q_a[4]_PORT_A_address_reg = DFFE(V1_q_a[4]_PORT_A_address, V1_q_a[4]_clock_0, , , );
V1_q_a[4]_clock_0 = GLOBAL(ALE);
V1_q_a[4]_PORT_A_data_out = MEMORY(, , V1_q_a[4]_PORT_A_address_reg, , , , , , V1_q_a[4]_clock_0, , , , , );
V1_q_a[0] = V1_q_a[4]_PORT_A_data_out[1];


--A1L145 is rtl~193 at LC_X16_Y12_N7
--operation mode is normal

A1L145 = V1_q_a[1] & (V1_q_a[0]);


--A1L142 is rtl~0 at LC_X16_Y14_N0
--operation mode is normal

A1L142 = V1_q_a[3] & A1L145 & V1_q_a[4] & V1_q_a[2];


--S1_SUM[18] is add18:inst47|SUM[18] at LC_X19_Y12_N9
--operation mode is normal

S1_SUM[18]_carry_eqn = (!S1L51 & S1L62) # (S1L51 & S1L63);
S1_SUM[18]_lut_out = S1_SUM[18] $ (!S1_SUM[18]_carry_eqn);
S1_SUM[18] = DFFEAS(S1_SUM[18]_lut_out, GLOBAL(K1_Cout), VCC, , S1L13, , , S1L66, );


--S1_SUM[8] is add18:inst47|SUM[8] at LC_X19_Y13_N9
--operation mode is arithmetic

S1_SUM[8]_carry_eqn = (!S1L23 & S1L34) # (S1L23 & S1L35);
S1_SUM[8]_lut_out = S1_SUM[8] $ (!S1_SUM[8]_carry_eqn);
S1_SUM[8] = DFFEAS(S1_SUM[8]_lut_out, GLOBAL(K1_Cout), VCC, , S1L13, , , S1L66, );

--S1L37 is add18:inst47|SUM[8]~275 at LC_X19_Y13_N9
--operation mode is arithmetic

S1L37 = CARRY(S1_SUM[8] & (!S1L35));


--U2_q_b[7] is RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[7] at M4K_X17_Y13
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
U2_q_b[7]_PORT_A_data_in = BUS(in2[7], in2[6], in2[4], in2[2]);
U2_q_b[7]_PORT_A_data_in_reg = DFFE(U2_q_b[7]_PORT_A_data_in, U2_q_b[7]_clock_0, , , U2_q_b[7]_clock_enable_0);
U2_q_b[7]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U2_q_b[7]_PORT_A_address_reg = DFFE(U2_q_b[7]_PORT_A_address, U2_q_b[7]_clock_0, , , U2_q_b[7]_clock_enable_0);
U2_q_b[7]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U2_q_b[7]_PORT_B_address_reg = DFFE(U2_q_b[7]_PORT_B_address, U2_q_b[7]_clock_1, , , );
U2_q_b[7]_PORT_A_write_enable = VCC;
U2_q_b[7]_PORT_A_write_enable_reg = DFFE(U2_q_b[7]_PORT_A_write_enable, U2_q_b[7]_clock_0, , , U2_q_b[7]_clock_enable_0);
U2_q_b[7]_PORT_B_read_enable = inst36;
U2_q_b[7]_PORT_B_read_enable_reg = DFFE(U2_q_b[7]_PORT_B_read_enable, U2_q_b[7]_clock_1, , , );
U2_q_b[7]_clock_0 = GLOBAL(CLK_40);
U2_q_b[7]_clock_1 = GLOBAL(CLK_40);
U2_q_b[7]_clock_enable_0 = inst37;
U2_q_b[7]_PORT_B_data_out = MEMORY(U2_q_b[7]_PORT_A_data_in_reg, , U2_q_b[7]_PORT_A_address_reg, U2_q_b[7]_PORT_B_address_reg, U2_q_b[7]_PORT_A_write_enable_reg, U2_q_b[7]_PORT_B_read_enable_reg, , , U2_q_b[7]_clock_0, U2_q_b[7]_clock_1, U2_q_b[7]_clock_enable_0, , , );
U2_q_b[7]_PORT_B_data_out_reg = DFFE(U2_q_b[7]_PORT_B_data_out, U2_q_b[7]_clock_1, , , );
U2_q_b[7] = U2_q_b[7]_PORT_B_data_out_reg[0];

--U2_q_b[2] is RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[2] at M4K_X17_Y13
U2_q_b[7]_PORT_A_data_in = BUS(in2[7], in2[6], in2[4], in2[2]);
U2_q_b[7]_PORT_A_data_in_reg = DFFE(U2_q_b[7]_PORT_A_data_in, U2_q_b[7]_clock_0, , , U2_q_b[7]_clock_enable_0);
U2_q_b[7]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U2_q_b[7]_PORT_A_address_reg = DFFE(U2_q_b[7]_PORT_A_address, U2_q_b[7]_clock_0, , , U2_q_b[7]_clock_enable_0);
U2_q_b[7]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U2_q_b[7]_PORT_B_address_reg = DFFE(U2_q_b[7]_PORT_B_address, U2_q_b[7]_clock_1, , , );
U2_q_b[7]_PORT_A_write_enable = VCC;
U2_q_b[7]_PORT_A_write_enable_reg = DFFE(U2_q_b[7]_PORT_A_write_enable, U2_q_b[7]_clock_0, , , U2_q_b[7]_clock_enable_0);
U2_q_b[7]_PORT_B_read_enable = inst36;
U2_q_b[7]_PORT_B_read_enable_reg = DFFE(U2_q_b[7]_PORT_B_read_enable, U2_q_b[7]_clock_1, , , );
U2_q_b[7]_clock_0 = GLOBAL(CLK_40);
U2_q_b[7]_clock_1 = GLOBAL(CLK_40);
U2_q_b[7]_clock_enable_0 = inst37;
U2_q_b[7]_PORT_B_data_out = MEMORY(U2_q_b[7]_PORT_A_data_in_reg, , U2_q_b[7]_PORT_A_address_reg, U2_q_b[7]_PORT_B_address_reg, U2_q_b[7]_PORT_A_write_enable_reg, U2_q_b[7]_PORT_B_read_enable_reg, , , U2_q_b[7]_clock_0, U2_q_b[7]_clock_1, U2_q_b[7]_clock_enable_0, , , );
U2_q_b[7]_PORT_B_data_out_reg = DFFE(U2_q_b[7]_PORT_B_data_out, U2_q_b[7]_clock_1, , , );
U2_q_b[2] = U2_q_b[7]_PORT_B_data_out_reg[3];

--U2_q_b[4] is RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[4] at M4K_X17_Y13
U2_q_b[7]_PORT_A_data_in = BUS(in2[7], in2[6], in2[4], in2[2]);
U2_q_b[7]_PORT_A_data_in_reg = DFFE(U2_q_b[7]_PORT_A_data_in, U2_q_b[7]_clock_0, , , U2_q_b[7]_clock_enable_0);
U2_q_b[7]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U2_q_b[7]_PORT_A_address_reg = DFFE(U2_q_b[7]_PORT_A_address, U2_q_b[7]_clock_0, , , U2_q_b[7]_clock_enable_0);
U2_q_b[7]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U2_q_b[7]_PORT_B_address_reg = DFFE(U2_q_b[7]_PORT_B_address, U2_q_b[7]_clock_1, , , );
U2_q_b[7]_PORT_A_write_enable = VCC;
U2_q_b[7]_PORT_A_write_enable_reg = DFFE(U2_q_b[7]_PORT_A_write_enable, U2_q_b[7]_clock_0, , , U2_q_b[7]_clock_enable_0);
U2_q_b[7]_PORT_B_read_enable = inst36;
U2_q_b[7]_PORT_B_read_enable_reg = DFFE(U2_q_b[7]_PORT_B_read_enable, U2_q_b[7]_clock_1, , , );
U2_q_b[7]_clock_0 = GLOBAL(CLK_40);
U2_q_b[7]_clock_1 = GLOBAL(CLK_40);
U2_q_b[7]_clock_enable_0 = inst37;
U2_q_b[7]_PORT_B_data_out = MEMORY(U2_q_b[7]_PORT_A_data_in_reg, , U2_q_b[7]_PORT_A_address_reg, U2_q_b[7]_PORT_B_address_reg, U2_q_b[7]_PORT_A_write_enable_reg, U2_q_b[7]_PORT_B_read_enable_reg, , , U2_q_b[7]_clock_0, U2_q_b[7]_clock_1, U2_q_b[7]_clock_enable_0, , , );
U2_q_b[7]_PORT_B_data_out_reg = DFFE(U2_q_b[7]_PORT_B_data_out, U2_q_b[7]_clock_1, , , );
U2_q_b[4] = U2_q_b[7]_PORT_B_data_out_reg[2];

--U2_q_b[6] is RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[6] at M4K_X17_Y13
U2_q_b[7]_PORT_A_data_in = BUS(in2[7], in2[6], in2[4], in2[2]);
U2_q_b[7]_PORT_A_data_in_reg = DFFE(U2_q_b[7]_PORT_A_data_in, U2_q_b[7]_clock_0, , , U2_q_b[7]_clock_enable_0);
U2_q_b[7]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U2_q_b[7]_PORT_A_address_reg = DFFE(U2_q_b[7]_PORT_A_address, U2_q_b[7]_clock_0, , , U2_q_b[7]_clock_enable_0);
U2_q_b[7]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U2_q_b[7]_PORT_B_address_reg = DFFE(U2_q_b[7]_PORT_B_address, U2_q_b[7]_clock_1, , , );
U2_q_b[7]_PORT_A_write_enable = VCC;
U2_q_b[7]_PORT_A_write_enable_reg = DFFE(U2_q_b[7]_PORT_A_write_enable, U2_q_b[7]_clock_0, , , U2_q_b[7]_clock_enable_0);
U2_q_b[7]_PORT_B_read_enable = inst36;
U2_q_b[7]_PORT_B_read_enable_reg = DFFE(U2_q_b[7]_PORT_B_read_enable, U2_q_b[7]_clock_1, , , );
U2_q_b[7]_clock_0 = GLOBAL(CLK_40);
U2_q_b[7]_clock_1 = GLOBAL(CLK_40);
U2_q_b[7]_clock_enable_0 = inst37;
U2_q_b[7]_PORT_B_data_out = MEMORY(U2_q_b[7]_PORT_A_data_in_reg, , U2_q_b[7]_PORT_A_address_reg, U2_q_b[7]_PORT_B_address_reg, U2_q_b[7]_PORT_A_write_enable_reg, U2_q_b[7]_PORT_B_read_enable_reg, , , U2_q_b[7]_clock_0, U2_q_b[7]_clock_1, U2_q_b[7]_clock_enable_0, , , );
U2_q_b[7]_PORT_B_data_out_reg = DFFE(U2_q_b[7]_PORT_B_data_out, U2_q_b[7]_clock_1, , , );
U2_q_b[6] = U2_q_b[7]_PORT_B_data_out_reg[1];


--U1_q_b[7] is RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[7] at M4K_X17_Y12
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
U1_q_b[7]_PORT_A_data_in = BUS(in1[7], in1[4], in1[3], in1[0]);
U1_q_b[7]_PORT_A_data_in_reg = DFFE(U1_q_b[7]_PORT_A_data_in, U1_q_b[7]_clock_0, , , U1_q_b[7]_clock_enable_0);
U1_q_b[7]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U1_q_b[7]_PORT_A_address_reg = DFFE(U1_q_b[7]_PORT_A_address, U1_q_b[7]_clock_0, , , U1_q_b[7]_clock_enable_0);
U1_q_b[7]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U1_q_b[7]_PORT_B_address_reg = DFFE(U1_q_b[7]_PORT_B_address, U1_q_b[7]_clock_1, , , );
U1_q_b[7]_PORT_A_write_enable = VCC;
U1_q_b[7]_PORT_A_write_enable_reg = DFFE(U1_q_b[7]_PORT_A_write_enable, U1_q_b[7]_clock_0, , , U1_q_b[7]_clock_enable_0);
U1_q_b[7]_PORT_B_read_enable = inst38;
U1_q_b[7]_PORT_B_read_enable_reg = DFFE(U1_q_b[7]_PORT_B_read_enable, U1_q_b[7]_clock_1, , , );
U1_q_b[7]_clock_0 = GLOBAL(CLK_40);
U1_q_b[7]_clock_1 = GLOBAL(CLK_40);
U1_q_b[7]_clock_enable_0 = inst37;
U1_q_b[7]_PORT_B_data_out = MEMORY(U1_q_b[7]_PORT_A_data_in_reg, , U1_q_b[7]_PORT_A_address_reg, U1_q_b[7]_PORT_B_address_reg, U1_q_b[7]_PORT_A_write_enable_reg, U1_q_b[7]_PORT_B_read_enable_reg, , , U1_q_b[7]_clock_0, U1_q_b[7]_clock_1, U1_q_b[7]_clock_enable_0, , , );
U1_q_b[7]_PORT_B_data_out_reg = DFFE(U1_q_b[7]_PORT_B_data_out, U1_q_b[7]_clock_1, , , );
U1_q_b[7] = U1_q_b[7]_PORT_B_data_out_reg[0];

--U1_q_b[0] is RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[0] at M4K_X17_Y12
U1_q_b[7]_PORT_A_data_in = BUS(in1[7], in1[4], in1[3], in1[0]);
U1_q_b[7]_PORT_A_data_in_reg = DFFE(U1_q_b[7]_PORT_A_data_in, U1_q_b[7]_clock_0, , , U1_q_b[7]_clock_enable_0);
U1_q_b[7]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U1_q_b[7]_PORT_A_address_reg = DFFE(U1_q_b[7]_PORT_A_address, U1_q_b[7]_clock_0, , , U1_q_b[7]_clock_enable_0);
U1_q_b[7]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U1_q_b[7]_PORT_B_address_reg = DFFE(U1_q_b[7]_PORT_B_address, U1_q_b[7]_clock_1, , , );
U1_q_b[7]_PORT_A_write_enable = VCC;
U1_q_b[7]_PORT_A_write_enable_reg = DFFE(U1_q_b[7]_PORT_A_write_enable, U1_q_b[7]_clock_0, , , U1_q_b[7]_clock_enable_0);
U1_q_b[7]_PORT_B_read_enable = inst38;
U1_q_b[7]_PORT_B_read_enable_reg = DFFE(U1_q_b[7]_PORT_B_read_enable, U1_q_b[7]_clock_1, , , );
U1_q_b[7]_clock_0 = GLOBAL(CLK_40);
U1_q_b[7]_clock_1 = GLOBAL(CLK_40);
U1_q_b[7]_clock_enable_0 = inst37;
U1_q_b[7]_PORT_B_data_out = MEMORY(U1_q_b[7]_PORT_A_data_in_reg, , U1_q_b[7]_PORT_A_address_reg, U1_q_b[7]_PORT_B_address_reg, U1_q_b[7]_PORT_A_write_enable_reg, U1_q_b[7]_PORT_B_read_enable_reg, , , U1_q_b[7]_clock_0, U1_q_b[7]_clock_1, U1_q_b[7]_clock_enable_0, , , );
U1_q_b[7]_PORT_B_data_out_reg = DFFE(U1_q_b[7]_PORT_B_data_out, U1_q_b[7]_clock_1, , , );
U1_q_b[0] = U1_q_b[7]_PORT_B_data_out_reg[3];

--U1_q_b[3] is RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[3] at M4K_X17_Y12
U1_q_b[7]_PORT_A_data_in = BUS(in1[7], in1[4], in1[3], in1[0]);
U1_q_b[7]_PORT_A_data_in_reg = DFFE(U1_q_b[7]_PORT_A_data_in, U1_q_b[7]_clock_0, , , U1_q_b[7]_clock_enable_0);
U1_q_b[7]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U1_q_b[7]_PORT_A_address_reg = DFFE(U1_q_b[7]_PORT_A_address, U1_q_b[7]_clock_0, , , U1_q_b[7]_clock_enable_0);
U1_q_b[7]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U1_q_b[7]_PORT_B_address_reg = DFFE(U1_q_b[7]_PORT_B_address, U1_q_b[7]_clock_1, , , );
U1_q_b[7]_PORT_A_write_enable = VCC;
U1_q_b[7]_PORT_A_write_enable_reg = DFFE(U1_q_b[7]_PORT_A_write_enable, U1_q_b[7]_clock_0, , , U1_q_b[7]_clock_enable_0);
U1_q_b[7]_PORT_B_read_enable = inst38;
U1_q_b[7]_PORT_B_read_enable_reg = DFFE(U1_q_b[7]_PORT_B_read_enable, U1_q_b[7]_clock_1, , , );
U1_q_b[7]_clock_0 = GLOBAL(CLK_40);
U1_q_b[7]_clock_1 = GLOBAL(CLK_40);
U1_q_b[7]_clock_enable_0 = inst37;
U1_q_b[7]_PORT_B_data_out = MEMORY(U1_q_b[7]_PORT_A_data_in_reg, , U1_q_b[7]_PORT_A_address_reg, U1_q_b[7]_PORT_B_address_reg, U1_q_b[7]_PORT_A_write_enable_reg, U1_q_b[7]_PORT_B_read_enable_reg, , , U1_q_b[7]_clock_0, U1_q_b[7]_clock_1, U1_q_b[7]_clock_enable_0, , , );
U1_q_b[7]_PORT_B_data_out_reg = DFFE(U1_q_b[7]_PORT_B_data_out, U1_q_b[7]_clock_1, , , );
U1_q_b[3] = U1_q_b[7]_PORT_B_data_out_reg[2];

--U1_q_b[4] is RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[4] at M4K_X17_Y12
U1_q_b[7]_PORT_A_data_in = BUS(in1[7], in1[4], in1[3], in1[0]);
U1_q_b[7]_PORT_A_data_in_reg = DFFE(U1_q_b[7]_PORT_A_data_in, U1_q_b[7]_clock_0, , , U1_q_b[7]_clock_enable_0);
U1_q_b[7]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U1_q_b[7]_PORT_A_address_reg = DFFE(U1_q_b[7]_PORT_A_address, U1_q_b[7]_clock_0, , , U1_q_b[7]_clock_enable_0);
U1_q_b[7]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U1_q_b[7]_PORT_B_address_reg = DFFE(U1_q_b[7]_PORT_B_address, U1_q_b[7]_clock_1, , , );
U1_q_b[7]_PORT_A_write_enable = VCC;
U1_q_b[7]_PORT_A_write_enable_reg = DFFE(U1_q_b[7]_PORT_A_write_enable, U1_q_b[7]_clock_0, , , U1_q_b[7]_clock_enable_0);
U1_q_b[7]_PORT_B_read_enable = inst38;
U1_q_b[7]_PORT_B_read_enable_reg = DFFE(U1_q_b[7]_PORT_B_read_enable, U1_q_b[7]_clock_1, , , );
U1_q_b[7]_clock_0 = GLOBAL(CLK_40);
U1_q_b[7]_clock_1 = GLOBAL(CLK_40);
U1_q_b[7]_clock_enable_0 = inst37;
U1_q_b[7]_PORT_B_data_out = MEMORY(U1_q_b[7]_PORT_A_data_in_reg, , U1_q_b[7]_PORT_A_address_reg, U1_q_b[7]_PORT_B_address_reg, U1_q_b[7]_PORT_A_write_enable_reg, U1_q_b[7]_PORT_B_read_enable_reg, , , U1_q_b[7]_clock_0, U1_q_b[7]_clock_1, U1_q_b[7]_clock_enable_0, , , );
U1_q_b[7]_PORT_B_data_out_reg = DFFE(U1_q_b[7]_PORT_B_data_out, U1_q_b[7]_clock_1, , , );
U1_q_b[4] = U1_q_b[7]_PORT_B_data_out_reg[1];


--D1L15 is select2_1:inst31|out_q[7]~984 at LC_X15_Y12_N9
--operation mode is normal

D1L15 = A1L130 & (U2_q_b[7]) # !A1L130 & U1_q_b[7];


--L1_out_q[7] is select_q:inst19|out_q[7] at LC_X15_Y12_N4
--operation mode is normal

L1_out_q[7]_lut_out = A1L130 & in2[7] # !A1L130 & (in1[7]);
L1_out_q[7] = DFFEAS(L1_out_q[7]_lut_out, GLOBAL(K3_Cout), VCC, , , , , , );


--D1L16 is select2_1:inst31|out_q[7]~985 at LC_X15_Y12_N7
--operation mode is normal

D1L16 = A1L128 & (D1L15) # !A1L128 & L1_out_q[7];


--U1_q_b[6] is RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[6] at M4K_X17_Y15
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
U1_q_b[6]_PORT_A_data_in = BUS(in1[6], in1[5], in1[2], in1[1]);
U1_q_b[6]_PORT_A_data_in_reg = DFFE(U1_q_b[6]_PORT_A_data_in, U1_q_b[6]_clock_0, , , U1_q_b[6]_clock_enable_0);
U1_q_b[6]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U1_q_b[6]_PORT_A_address_reg = DFFE(U1_q_b[6]_PORT_A_address, U1_q_b[6]_clock_0, , , U1_q_b[6]_clock_enable_0);
U1_q_b[6]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U1_q_b[6]_PORT_B_address_reg = DFFE(U1_q_b[6]_PORT_B_address, U1_q_b[6]_clock_1, , , );
U1_q_b[6]_PORT_A_write_enable = VCC;
U1_q_b[6]_PORT_A_write_enable_reg = DFFE(U1_q_b[6]_PORT_A_write_enable, U1_q_b[6]_clock_0, , , U1_q_b[6]_clock_enable_0);
U1_q_b[6]_PORT_B_read_enable = inst38;
U1_q_b[6]_PORT_B_read_enable_reg = DFFE(U1_q_b[6]_PORT_B_read_enable, U1_q_b[6]_clock_1, , , );
U1_q_b[6]_clock_0 = GLOBAL(CLK_40);
U1_q_b[6]_clock_1 = GLOBAL(CLK_40);
U1_q_b[6]_clock_enable_0 = inst37;
U1_q_b[6]_PORT_B_data_out = MEMORY(U1_q_b[6]_PORT_A_data_in_reg, , U1_q_b[6]_PORT_A_address_reg, U1_q_b[6]_PORT_B_address_reg, U1_q_b[6]_PORT_A_write_enable_reg, U1_q_b[6]_PORT_B_read_enable_reg, , , U1_q_b[6]_clock_0, U1_q_b[6]_clock_1, U1_q_b[6]_clock_enable_0, , , );
U1_q_b[6]_PORT_B_data_out_reg = DFFE(U1_q_b[6]_PORT_B_data_out, U1_q_b[6]_clock_1, , , );
U1_q_b[6] = U1_q_b[6]_PORT_B_data_out_reg[0];

--U1_q_b[1] is RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[1] at M4K_X17_Y15
U1_q_b[6]_PORT_A_data_in = BUS(in1[6], in1[5], in1[2], in1[1]);
U1_q_b[6]_PORT_A_data_in_reg = DFFE(U1_q_b[6]_PORT_A_data_in, U1_q_b[6]_clock_0, , , U1_q_b[6]_clock_enable_0);
U1_q_b[6]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U1_q_b[6]_PORT_A_address_reg = DFFE(U1_q_b[6]_PORT_A_address, U1_q_b[6]_clock_0, , , U1_q_b[6]_clock_enable_0);
U1_q_b[6]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U1_q_b[6]_PORT_B_address_reg = DFFE(U1_q_b[6]_PORT_B_address, U1_q_b[6]_clock_1, , , );
U1_q_b[6]_PORT_A_write_enable = VCC;
U1_q_b[6]_PORT_A_write_enable_reg = DFFE(U1_q_b[6]_PORT_A_write_enable, U1_q_b[6]_clock_0, , , U1_q_b[6]_clock_enable_0);
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