core_1c6.fit.rpt

运用TLC5510A高速(20M),扫描出波形,测量相位差,两个TLC5510A测两个波形.

Fitter report for core_1c6
Sun Dec 03 16:18:15 2006
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Fitter Equations
  6. Pin-Out File
  7. Fitter Resource Usage Summary
  8. Input Pins
  9. Output Pins
 10. Bidir Pins
 11. I/O Bank Usage
 12. All Package Pins
 13. Output Pin Default Load For Reported TCO
 14. Fitter Resource Utilization by Entity
 15. Delay Chain Summary
 16. Pad To Core Delay Chain Fanout
 17. Control Signals
 18. Global & Other Fast Signals
 19. Non-Global High Fan-Out Signals
 20. Fitter RAM Summary
 21. Interconnect Usage Summary
 22. LAB Logic Elements
 23. LAB-wide Signals
 24. LAB Signals Sourced
 25. LAB Signals Sourced Out
 26. LAB Distinct Inputs
 27. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------+
; Fitter Summary                                                   ;
+-----------------------+------------------------------------------+
; Fitter Status         ; Successful - Sun Dec 03 16:18:15 2006    ;
; Quartus II Version    ; 5.1 Build 176 10/26/2005 SJ Full Version ;
; Revision Name         ; core_1c6                                 ;
; Top-level Entity Name ; core_1c6                                 ;
; Family                ; Cyclone                                  ;
; Device                ; EP1C6Q240C8                              ;
; Timing Models         ; Final                                    ;
; Total logic elements  ; 174 / 5,980 ( 3 % )                      ;
; Total pins            ; 97 / 185 ( 52 % )                        ;
; Total virtual pins    ; 0                                        ;
; Total memory bits     ; 18,944 / 92,160 ( 21 % )                 ;
; Total PLLs            ; 0 / 2 ( 0 % )                            ;
+-----------------------+------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                        ;
+------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                               ; Setting                        ; Default Value                  ;
+------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                               ; EP1C6Q240C8                    ;                                ;
; SignalProbe signals routed during normal compilation ; Off                            ; Off                            ;
; Use smart compilation                                ; Off                            ; Off                            ;
; Router Timing Optimization Level                     ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                          ; 1.0                            ; 1.0                            ;