core_1c6.map.eqn

运用TLC5510A高速(20M),扫描出波形,测量相位差,两个TLC5510A测两个波形.

U2_q_b[4]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U2_q_b[4]_PORT_B_address_reg = DFFE(U2_q_b[4]_PORT_B_address, U2_q_b[4]_clock_1, , , );
U2_q_b[4]_PORT_A_write_enable = VCC;
U2_q_b[4]_PORT_A_write_enable_reg = DFFE(U2_q_b[4]_PORT_A_write_enable, U2_q_b[4]_clock_0, , , U2_q_b[4]_clock_enable_0);
U2_q_b[4]_PORT_B_read_enable = inst36;
U2_q_b[4]_PORT_B_read_enable_reg = DFFE(U2_q_b[4]_PORT_B_read_enable, U2_q_b[4]_clock_1, , , );
U2_q_b[4]_clock_0 = CLK_40;
U2_q_b[4]_clock_1 = CLK_40;
U2_q_b[4]_clock_enable_0 = inst37;
U2_q_b[4]_PORT_B_data_out = MEMORY(U2_q_b[4]_PORT_A_data_in_reg, , U2_q_b[4]_PORT_A_address_reg, U2_q_b[4]_PORT_B_address_reg, U2_q_b[4]_PORT_A_write_enable_reg, U2_q_b[4]_PORT_B_read_enable_reg, , , U2_q_b[4]_clock_0, U2_q_b[4]_clock_1, U2_q_b[4]_clock_enable_0, , , );
U2_q_b[4]_PORT_B_data_out_reg = DFFE(U2_q_b[4]_PORT_B_data_out, U2_q_b[4]_clock_1, , , );
U2_q_b[4] = U2_q_b[4]_PORT_B_data_out_reg[0];


--U1_q_b[4] is RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
U1_q_b[4]_PORT_A_data_in = in1[4];
U1_q_b[4]_PORT_A_data_in_reg = DFFE(U1_q_b[4]_PORT_A_data_in, U1_q_b[4]_clock_0, , , U1_q_b[4]_clock_enable_0);
U1_q_b[4]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U1_q_b[4]_PORT_A_address_reg = DFFE(U1_q_b[4]_PORT_A_address, U1_q_b[4]_clock_0, , , U1_q_b[4]_clock_enable_0);
U1_q_b[4]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U1_q_b[4]_PORT_B_address_reg = DFFE(U1_q_b[4]_PORT_B_address, U1_q_b[4]_clock_1, , , );
U1_q_b[4]_PORT_A_write_enable = VCC;
U1_q_b[4]_PORT_A_write_enable_reg = DFFE(U1_q_b[4]_PORT_A_write_enable, U1_q_b[4]_clock_0, , , U1_q_b[4]_clock_enable_0);
U1_q_b[4]_PORT_B_read_enable = inst38;
U1_q_b[4]_PORT_B_read_enable_reg = DFFE(U1_q_b[4]_PORT_B_read_enable, U1_q_b[4]_clock_1, , , );
U1_q_b[4]_clock_0 = CLK_40;
U1_q_b[4]_clock_1 = CLK_40;
U1_q_b[4]_clock_enable_0 = inst37;
U1_q_b[4]_PORT_B_data_out = MEMORY(U1_q_b[4]_PORT_A_data_in_reg, , U1_q_b[4]_PORT_A_address_reg, U1_q_b[4]_PORT_B_address_reg, U1_q_b[4]_PORT_A_write_enable_reg, U1_q_b[4]_PORT_B_read_enable_reg, , , U1_q_b[4]_clock_0, U1_q_b[4]_clock_1, U1_q_b[4]_clock_enable_0, , , );
U1_q_b[4]_PORT_B_data_out_reg = DFFE(U1_q_b[4]_PORT_B_data_out, U1_q_b[4]_clock_1, , , );
U1_q_b[4] = U1_q_b[4]_PORT_B_data_out_reg[0];


--D1L9 is select2_1:inst31|out_q[4]~990
--operation mode is normal

D1L9 = A1L130 & U2_q_b[4] # !A1L130 & (U1_q_b[4]);


--L1_out_q[4] is select_q:inst19|out_q[4]
--operation mode is normal

L1_out_q[4]_lut_out = A1L130 & in2[4] # !A1L130 & (in1[4]);
L1_out_q[4] = DFFEAS(L1_out_q[4]_lut_out, K3_Cout, VCC, , , , , , );


--D1L10 is select2_1:inst31|out_q[4]~991
--operation mode is normal

D1L10 = A1L128 & D1L9 # !A1L128 & (L1_out_q[4]);


--U2_q_b[3] is RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
U2_q_b[3]_PORT_A_data_in = in2[3];
U2_q_b[3]_PORT_A_data_in_reg = DFFE(U2_q_b[3]_PORT_A_data_in, U2_q_b[3]_clock_0, , , U2_q_b[3]_clock_enable_0);
U2_q_b[3]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U2_q_b[3]_PORT_A_address_reg = DFFE(U2_q_b[3]_PORT_A_address, U2_q_b[3]_clock_0, , , U2_q_b[3]_clock_enable_0);
U2_q_b[3]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U2_q_b[3]_PORT_B_address_reg = DFFE(U2_q_b[3]_PORT_B_address, U2_q_b[3]_clock_1, , , );
U2_q_b[3]_PORT_A_write_enable = VCC;
U2_q_b[3]_PORT_A_write_enable_reg = DFFE(U2_q_b[3]_PORT_A_write_enable, U2_q_b[3]_clock_0, , , U2_q_b[3]_clock_enable_0);
U2_q_b[3]_PORT_B_read_enable = inst36;
U2_q_b[3]_PORT_B_read_enable_reg = DFFE(U2_q_b[3]_PORT_B_read_enable, U2_q_b[3]_clock_1, , , );
U2_q_b[3]_clock_0 = CLK_40;
U2_q_b[3]_clock_1 = CLK_40;
U2_q_b[3]_clock_enable_0 = inst37;
U2_q_b[3]_PORT_B_data_out = MEMORY(U2_q_b[3]_PORT_A_data_in_reg, , U2_q_b[3]_PORT_A_address_reg, U2_q_b[3]_PORT_B_address_reg, U2_q_b[3]_PORT_A_write_enable_reg, U2_q_b[3]_PORT_B_read_enable_reg, , , U2_q_b[3]_clock_0, U2_q_b[3]_clock_1, U2_q_b[3]_clock_enable_0, , , );
U2_q_b[3]_PORT_B_data_out_reg = DFFE(U2_q_b[3]_PORT_B_data_out, U2_q_b[3]_clock_1, , , );
U2_q_b[3] = U2_q_b[3]_PORT_B_data_out_reg[0];


--U1_q_b[3] is RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
U1_q_b[3]_PORT_A_data_in = in1[3];
U1_q_b[3]_PORT_A_data_in_reg = DFFE(U1_q_b[3]_PORT_A_data_in, U1_q_b[3]_clock_0, , , U1_q_b[3]_clock_enable_0);
U1_q_b[3]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U1_q_b[3]_PORT_A_address_reg = DFFE(U1_q_b[3]_PORT_A_address, U1_q_b[3]_clock_0, , , U1_q_b[3]_clock_enable_0);
U1_q_b[3]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U1_q_b[3]_PORT_B_address_reg = DFFE(U1_q_b[3]_PORT_B_address, U1_q_b[3]_clock_1, , , );
U1_q_b[3]_PORT_A_write_enable = VCC;
U1_q_b[3]_PORT_A_write_enable_reg = DFFE(U1_q_b[3]_PORT_A_write_enable, U1_q_b[3]_clock_0, , , U1_q_b[3]_clock_enable_0);
U1_q_b[3]_PORT_B_read_enable = inst38;
U1_q_b[3]_PORT_B_read_enable_reg = DFFE(U1_q_b[3]_PORT_B_read_enable, U1_q_b[3]_clock_1, , , );
U1_q_b[3]_clock_0 = CLK_40;
U1_q_b[3]_clock_1 = CLK_40;
U1_q_b[3]_clock_enable_0 = inst37;
U1_q_b[3]_PORT_B_data_out = MEMORY(U1_q_b[3]_PORT_A_data_in_reg, , U1_q_b[3]_PORT_A_address_reg, U1_q_b[3]_PORT_B_address_reg, U1_q_b[3]_PORT_A_write_enable_reg, U1_q_b[3]_PORT_B_read_enable_reg, , , U1_q_b[3]_clock_0, U1_q_b[3]_clock_1, U1_q_b[3]_clock_enable_0, , , );
U1_q_b[3]_PORT_B_data_out_reg = DFFE(U1_q_b[3]_PORT_B_data_out, U1_q_b[3]_clock_1, , , );
U1_q_b[3] = U1_q_b[3]_PORT_B_data_out_reg[0];


--D1L7 is select2_1:inst31|out_q[3]~992
--operation mode is normal

D1L7 = A1L130 & U2_q_b[3] # !A1L130 & (U1_q_b[3]);


--L1_out_q[3] is select_q:inst19|out_q[3]
--operation mode is normal

L1_out_q[3]_lut_out = A1L130 & in2[3] # !A1L130 & (in1[3]);
L1_out_q[3] = DFFEAS(L1_out_q[3]_lut_out, K3_Cout, VCC, , , , , , );


--D1L8 is select2_1:inst31|out_q[3]~993
--operation mode is normal

D1L8 = A1L128 & D1L7 # !A1L128 & (L1_out_q[3]);


--U2_q_b[2] is RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
U2_q_b[2]_PORT_A_data_in = in2[2];
U2_q_b[2]_PORT_A_data_in_reg = DFFE(U2_q_b[2]_PORT_A_data_in, U2_q_b[2]_clock_0, , , U2_q_b[2]_clock_enable_0);
U2_q_b[2]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U2_q_b[2]_PORT_A_address_reg = DFFE(U2_q_b[2]_PORT_A_address, U2_q_b[2]_clock_0, , , U2_q_b[2]_clock_enable_0);
U2_q_b[2]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U2_q_b[2]_PORT_B_address_reg = DFFE(U2_q_b[2]_PORT_B_address, U2_q_b[2]_clock_1, , , );
U2_q_b[2]_PORT_A_write_enable = VCC;
U2_q_b[2]_PORT_A_write_enable_reg = DFFE(U2_q_b[2]_PORT_A_write_enable, U2_q_b[2]_clock_0, , , U2_q_b[2]_clock_enable_0);
U2_q_b[2]_PORT_B_read_enable = inst36;
U2_q_b[2]_PORT_B_read_enable_reg = DFFE(U2_q_b[2]_PORT_B_read_enable, U2_q_b[2]_clock_1, , , );
U2_q_b[2]_clock_0 = CLK_40;
U2_q_b[2]_clock_1 = CLK_40;
U2_q_b[2]_clock_enable_0 = inst37;
U2_q_b[2]_PORT_B_data_out = MEMORY(U2_q_b[2]_PORT_A_data_in_reg, , U2_q_b[2]_PORT_A_address_reg, U2_q_b[2]_PORT_B_address_reg, U2_q_b[2]_PORT_A_write_enable_reg, U2_q_b[2]_PORT_B_read_enable_reg, , , U2_q_b[2]_clock_0, U2_q_b[2]_clock_1, U2_q_b[2]_clock_enable_0, , , );
U2_q_b[2]_PORT_B_data_out_reg = DFFE(U2_q_b[2]_PORT_B_data_out, U2_q_b[2]_clock_1, , , );
U2_q_b[2] = U2_q_b[2]_PORT_B_data_out_reg[0];


--U1_q_b[2] is RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
U1_q_b[2]_PORT_A_data_in = in1[2];
U1_q_b[2]_PORT_A_data_in_reg = DFFE(U1_q_b[2]_PORT_A_data_in, U1_q_b[2]_clock_0, , , U1_q_b[2]_clock_enable_0);
U1_q_b[2]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U1_q_b[2]_PORT_A_address_reg = DFFE(U1_q_b[2]_PORT_A_address, U1_q_b[2]_clock_0, , , U1_q_b[2]_clock_enable_0);
U1_q_b[2]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U1_q_b[2]_PORT_B_address_reg = DFFE(U1_q_b[2]_PORT_B_address, U1_q_b[2]_clock_1, , , );
U1_q_b[2]_PORT_A_write_enable = VCC;
U1_q_b[2]_PORT_A_write_enable_reg = DFFE(U1_q_b[2]_PORT_A_write_enable, U1_q_b[2]_clock_0, , , U1_q_b[2]_clock_enable_0);
U1_q_b[2]_PORT_B_read_enable = inst38;
U1_q_b[2]_PORT_B_read_enable_reg = DFFE(U1_q_b[2]_PORT_B_read_enable, U1_q_b[2]_clock_1, , , );
U1_q_b[2]_clock_0 = CLK_40;
U1_q_b[2]_clock_1 = CLK_40;
U1_q_b[2]_clock_enable_0 = inst37;
U1_q_b[2]_PORT_B_data_out = MEMORY(U1_q_b[2]_PORT_A_data_in_reg, , U1_q_b[2]_PORT_A_address_reg, U1_q_b[2]_PORT_B_address_reg, U1_q_b[2]_PORT_A_write_enable_reg, U1_q_b[2]_PORT_B_read_enable_reg, , , U1_q_b[2]_clock_0, U1_q_b[2]_clock_1, U1_q_b[2]_clock_enable_0, , , );
U1_q_b[2]_PORT_B_data_out_reg = DFFE(U1_q_b[2]_PORT_B_data_out, U1_q_b[2]_clock_1, , , );
U1_q_b[2] = U1_q_b[2]_PORT_B_data_out_reg[0];


--D1L5 is select2_1:inst31|out_q[2]~994
--operation mode is normal

D1L5 = A1L130 & U2_q_b[2] # !A1L130 & (U1_q_b[2]);


--L1_out_q[2] is select_q:inst19|out_q[2]
--operation mode is normal

L1_out_q[2]_lut_out = A1L130 & in2[2] # !A1L130 & (in1[2]);
L1_out_q[2] = DFFEAS(L1_out_q[2]_lut_out, K3_Cout, VCC, , , , , , );


--D1L6 is select2_1:inst31|out_q[2]~995
--operation mode is normal

D1L6 = A1L128 & D1L5 # !A1L128 & (L1_out_q[2]);


--U2_q_b[1] is RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
U2_q_b[1]_PORT_A_data_in = in2[1];
U2_q_b[1]_PORT_A_data_in_reg = DFFE(U2_q_b[1]_PORT_A_data_in, U2_q_b[1]_clock_0, , , U2_q_b[1]_clock_enable_0);
U2_q_b[1]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U2_q_b[1]_PORT_A_address_reg = DFFE(U2_q_b[1]_PORT_A_address, U2_q_b[1]_clock_0, , , U2_q_b[1]_clock_enable_0);
U2_q_b[1]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U2_q_b[1]_PORT_B_address_reg = DFFE(U2_q_b[1]_PORT_B_address, U2_q_b[1]_clock_1, , , );
U2_q_b[1]_PORT_A_write_enable = VCC;
U2_q_b[1]_PORT_A_write_enable_reg = DFFE(U2_q_b[1]_PORT_A_write_enable, U2_q_b[1]_clock_0, , , U2_q_b[1]_clock_enable_0);
U2_q_b[1]_PORT_B_read_enable = inst36;
U2_q_b[1]_PORT_B_read_enable_reg = DFFE(U2_q_b[1]_PORT_B_read_enable, U2_q_b[1]_clock_1, , , );
U2_q_b[1]_clock_0 = CLK_40;
U2_q_b[1]_clock_1 = CLK_40;
U2_q_b[1]_clock_enable_0 = inst37;
U2_q_b[1]_PORT_B_data_out = MEMORY(U2_q_b[1]_PORT_A_data_in_reg, , U2_q_b[1]_PORT_A_address_reg, U2_q_b[1]_PORT_B_address_reg, U2_q_b[1]_PORT_A_write_enable_reg, U2_q_b[1]_PORT_B_read_enable_reg, , , U2_q_b[1]_clock_0, U2_q_b[1]_clock_1, U2_q_b[1]_clock_enable_0, , , );
U2_q_b[1]_PORT_B_data_out_reg = DFFE(U2_q_b[1]_PORT_B_data_out, U2_q_b[1]_clock_1, , , );
U2_q_b[1] = U2_q_b[1]_PORT_B_data_out_reg[0];


--U1_q_b[1] is RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
U1_q_b[1]_PORT_A_data_in = in1[1];
U1_q_b[1]_PORT_A_data_in_reg = DFFE(U1_q_b[1]_PORT_A_data_in, U1_q_b[1]_clock_0, , , U1_q_b[1]_clock_enable_0);
U1_q_b[1]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U1_q_b[1]_PORT_A_address_reg = DFFE(U1_q_b[1]_PORT_A_address, U1_q_b[1]_clock_0, , , U1_q_b[1]_clock_enable_0);
U1_q_b[1]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U1_q_b[1]_PORT_B_address_reg = DFFE(U1_q_b[1]_PORT_B_address, U1_q_b[1]_clock_1, , , );
U1_q_b[1]_PORT_A_write_enable = VCC;
U1_q_b[1]_PORT_A_write_enable_reg = DFFE(U1_q_b[1]_PORT_A_write_enable, U1_q_b[1]_clock_0, , , U1_q_b[1]_clock_enable_0);
U1_q_b[1]_PORT_B_read_enable = inst38;
U1_q_b[1]_PORT_B_read_enable_reg = DFFE(U1_q_b[1]_PORT_B_read_enable, U1_q_b[1]_clock_1, , , );
U1_q_b[1]_clock_0 = CLK_40;
U1_q_b[1]_clock_1 = CLK_40;
U1_q_b[1]_clock_enable_0 = inst37;
U1_q_b[1]_PORT_B_data_out = MEMORY(U1_q_b[1]_PORT_A_data_in_reg, , U1_q_b[1]_PORT_A_address_reg, U1_q_b[1]_PORT_B_address_reg, U1_q_b[1]_PORT_A_write_enable_reg, U1_q_b[1]_PORT_B_read_enable_reg, , , U1_q_b[1]_clock_0, U1_q_b[1]_clock_1, U1_q_b[1]_clock_enable_0, , , );
U1_q_b[1]_PORT_B_data_out_reg = DFFE(U1_q_b[1]_PORT_B_data_out, U1_q_b[1]_clock_1, , , );
U1_q_b[1] = U1_q_b[1]_PORT_B_data_out_reg[0];


--D1L3 is select2_1:inst31|out_q[1]~996
--operation mode is normal

D1L3 = A1L130 & U2_q_b[1] # !A1L130 & (U1_q_b[1]);


--L1_out_q[1] is select_q:inst19|out_q[1]
--operation mode is normal

L1_out_q[1]_lut_out = A1L130 & in2[1] # !A1L130 & (in1[1]);
L1_out_q[1] = DFFEAS(L1_out_q[1]_lut_out, K3_Cout, VCC, , , , , , );


--D1L4 is select2_1:inst31|out_q[1]~997
--operation mode is normal

D1L4 = A1L128 & D1L3 # !A1L128 & (L1_out_q[1]);


--U2_q_b[0] is RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
U2_q_b[0]_PORT_A_data_in = in2[0];
U2_q_b[0]_PORT_A_data_in_reg = DFFE(U2_q_b[0]_PORT_A_data_in, U2_q_b[0]_clock_0, , , U2_q_b[0]_clock_enable_0);
U2_q_b[0]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U2_q_b[0]_PORT_A_address_reg = DFFE(U2_q_b[0]_PORT_A_address, U2_q_b[0]_clock_0, , , U2_q_b[0]_clock_enable_0);
U2_q_b[0]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U2_q_b[0]_PORT_B_address_reg = DFFE(U2_q_b[0]_PORT_B_address, U2_q_b[0]_clock_1, , , );
U2_q_b[0]_PORT_A_write_enable = VCC;
U2_q_b[0]_PORT_A_write_enable_reg = DFFE(U2_q_b[0]_PORT_A_write_enable, U2_q_b[0]_clock_0, , , U2_q_b[0]_clock_enable_0);
U2_q_b[0]_PORT_B_read_enable = inst36;
U2_q_b[0]_PORT_B_read_enable_reg = DFFE(U2_q_b[0]_PORT_B_read_enable, U2_q_b[0]_clock_1, , , );
U2_q_b[0]_clock_0 = CLK_40;
U2_q_b[0]_clock_1 = CLK_40;
U2_q_b[0]_clock_enable_0 = inst37;
U2_q_b[0]_PORT_B_data_out = MEMORY(U2_q_b[0]_PORT_A_data_in_reg, , U2_q_b[0]_PORT_A_address_reg, U2_q_b[0]_PORT_B_address_reg, U2_q_b[0]_PORT_A_write_enable_reg, U2_q_b[0]_PORT_B_read_enable_reg, , , U2_q_b[0]_clock_0, U2_q_b[0]_clock_1, U2_q_b[0]_clock_enable_0, , , );
U2_q_b[0]_PORT_B_data_out_reg = DFFE(U2_q_b[0]_PORT_B_data_out, U2_q_b[0]_clock_1, , , );
U2_q_b[0] = U2_q_b[0]_PORT_B_data_out_reg[0];


--U1_q_b[0] is RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
U1_q_b[0]_PORT_A_data_in = in1[0];
U1_q_b[0]_PORT_A_data_in_reg = DFFE(U1_q_b[0]_PORT_A_data_in, U1_q_b[0]_clock_0, , , U1_q_b[0]_clock_enable_0);
U1_q_b[0]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U1_q_b[0]_PORT_A_address_reg = DFFE(U1_q_b[0]_PORT_A_address, U1_q_b[0]_clock_0, , , U1_q_b[0]_clock_enable_0);
U1_q_b[0]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U1_q_b[0]_PORT_B_address_reg = DFFE(U1_q_b[0]_PORT_B_address, U1_q_b[0]_clock_1, , , );
U1_q_b[0]_PORT_A_write_enable = VCC;
U1_q_b[0]_PORT_A_write_enable_reg = DFFE(U1_q_b[0]_PORT_A_write_enable, U1_q_b[0]_clock_0, , , U1_q_b[0]_clock_enable_0);
U1_q_b[0]_PORT_B_read_enable = inst38;
U1_q_b[0]_PORT_B_read_enable_reg = DFFE(U1_q_b[0]_PORT_B_read_enable, U1_q_b[0]_clock_1, , , );
U1_q_b[0]_clock_0 = CLK_40;
U1_q_b[0]_clock_1 = CLK_40;
U1_q_b[0]_clock_enable_0 = inst37;
U1_q_b[0]_PORT_B_data_out = MEMORY(U1_q_b[0]_PORT_A_data_in_reg, , U1_q_b[0]_PORT_A_address_reg, U1_q_b[0]_PORT_B_address_reg, U1_q_b[0]_PORT_A_write_enable_reg, U1_q_b[0]_PORT_B_read_enable_reg, , , U1_q_b[0]_clock_0, U1_q_b[0]_clock_1, U1_q_b[0]_clock_enable_0, , , );
U1_q_b[0]_PORT_B_data_out_reg = DFFE(U1_q_b[0]_PORT_B_data_out, U1_q_b[0]_clock_1, , , );
U1_q_b[0] = U1_q_b[0]_PORT_B_data_out_reg[0];


--D1L1 is select2_1:inst31|out_q[0]~998
--operation mode is normal

D1L1 = A1L130 & U2_q_b[0] # !A1L130 & (U1_q_b[0]);


--L1_out_q[0] is select_q:inst19|out_q[0]
--operation mode is normal

L1_out_q[0]_lut_out = A1L130 & in2[0] # !A1L130 & (in1[0]);
L1_out_q[0] = DFFEAS(L1_out_q[0]_lut_out, K3_Cout, VCC, , , , , , );


--D1L2 is select2_1:inst31|out_q[0]~999
--operation mode is normal

D1L2 = A1L128 & D1L1 # !A1L128 & (L1_out_q[0]);


--J1_KR_temp[0] is ScanKey:inst15|KR_temp[0]
--operation mode is normal

J1_KR_temp[0]_lut_out = A1L55;
J1_KR_temp[0] = DFFEAS(J1_KR_temp[0]_lut_out, ALE, VCC, , !A1L143, , , , );


--J1_KR_temp[1] is ScanKey:inst15|KR_temp[1]
--operation mode is normal

J1_KR_temp[1]_lut_out = A1L54;
J1_KR_temp[1] = DFFEAS(J1_KR_temp[1]_lut_out, ALE, VCC, , !A1L143, , , , );