core_1c6.map.eqn

运用TLC5510A高速(20M),扫描出波形,测量相位差,两个TLC5510A测两个波形.

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--E1L11 is BUS_Connect:inst9|Select~459
--operation mode is normal

E1L11 = P2[3] & P2[4] & (!P2[6]);


--R1L1 is Adr4_16:inst45|CSout[3]~67
--operation mode is normal

R1L1 = P2[5] # !E1L11 # !P2[7];


--V1_q_a[4] is ScanKey:inst15|altsyncram:reduce_or_rtl_0|altsyncram_r9l:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 5
--Port A Input: Registered, Port A Output: Un-registered
V1_q_a[4]_PORT_A_address = BUS(J1_KR_temp[0], J1_KR_temp[1], J1_KR_temp[2], J1_KR_temp[3], J1_KR_temp[4], J1_KR_temp[5], J1_KC_temp[0], J1_KC_temp[1], J1_KC_temp[2]);
V1_q_a[4]_PORT_A_address_reg = DFFE(V1_q_a[4]_PORT_A_address, V1_q_a[4]_clock_0, , , );
V1_q_a[4]_clock_0 = ALE;
V1_q_a[4]_PORT_A_data_out = MEMORY(, , V1_q_a[4]_PORT_A_address_reg, , , , , , V1_q_a[4]_clock_0, , , , , );
V1_q_a[4] = V1_q_a[4]_PORT_A_data_out[0];


--V1_q_a[0] is ScanKey:inst15|altsyncram:reduce_or_rtl_0|altsyncram_r9l:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 5
--Port A Input: Registered, Port A Output: Un-registered
V1_q_a[0]_PORT_A_address = BUS(J1_KR_temp[0], J1_KR_temp[1], J1_KR_temp[2], J1_KR_temp[3], J1_KR_temp[4], J1_KR_temp[5], J1_KC_temp[0], J1_KC_temp[1], J1_KC_temp[2]);
V1_q_a[0]_PORT_A_address_reg = DFFE(V1_q_a[0]_PORT_A_address, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_clock_0 = ALE;
V1_q_a[0]_PORT_A_data_out = MEMORY(, , V1_q_a[0]_PORT_A_address_reg, , , , , , V1_q_a[0]_clock_0, , , , , );
V1_q_a[0] = V1_q_a[0]_PORT_A_data_out[0];


--V1_q_a[1] is ScanKey:inst15|altsyncram:reduce_or_rtl_0|altsyncram_r9l:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 5
--Port A Input: Registered, Port A Output: Un-registered
V1_q_a[1]_PORT_A_address = BUS(J1_KR_temp[0], J1_KR_temp[1], J1_KR_temp[2], J1_KR_temp[3], J1_KR_temp[4], J1_KR_temp[5], J1_KC_temp[0], J1_KC_temp[1], J1_KC_temp[2]);
V1_q_a[1]_PORT_A_address_reg = DFFE(V1_q_a[1]_PORT_A_address, V1_q_a[1]_clock_0, , , );
V1_q_a[1]_clock_0 = ALE;
V1_q_a[1]_PORT_A_data_out = MEMORY(, , V1_q_a[1]_PORT_A_address_reg, , , , , , V1_q_a[1]_clock_0, , , , , );
V1_q_a[1] = V1_q_a[1]_PORT_A_data_out[0];


--A1L145 is rtl~193
--operation mode is normal

A1L145 = V1_q_a[0] & V1_q_a[1];


--V1_q_a[2] is ScanKey:inst15|altsyncram:reduce_or_rtl_0|altsyncram_r9l:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 5
--Port A Input: Registered, Port A Output: Un-registered
V1_q_a[2]_PORT_A_address = BUS(J1_KR_temp[0], J1_KR_temp[1], J1_KR_temp[2], J1_KR_temp[3], J1_KR_temp[4], J1_KR_temp[5], J1_KC_temp[0], J1_KC_temp[1], J1_KC_temp[2]);
V1_q_a[2]_PORT_A_address_reg = DFFE(V1_q_a[2]_PORT_A_address, V1_q_a[2]_clock_0, , , );
V1_q_a[2]_clock_0 = ALE;
V1_q_a[2]_PORT_A_data_out = MEMORY(, , V1_q_a[2]_PORT_A_address_reg, , , , , , V1_q_a[2]_clock_0, , , , , );
V1_q_a[2] = V1_q_a[2]_PORT_A_data_out[0];


--V1_q_a[3] is ScanKey:inst15|altsyncram:reduce_or_rtl_0|altsyncram_r9l:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 5
--Port A Input: Registered, Port A Output: Un-registered
V1_q_a[3]_PORT_A_address = BUS(J1_KR_temp[0], J1_KR_temp[1], J1_KR_temp[2], J1_KR_temp[3], J1_KR_temp[4], J1_KR_temp[5], J1_KC_temp[0], J1_KC_temp[1], J1_KC_temp[2]);
V1_q_a[3]_PORT_A_address_reg = DFFE(V1_q_a[3]_PORT_A_address, V1_q_a[3]_clock_0, , , );
V1_q_a[3]_clock_0 = ALE;
V1_q_a[3]_PORT_A_data_out = MEMORY(, , V1_q_a[3]_PORT_A_address_reg, , , , , , V1_q_a[3]_clock_0, , , , , );
V1_q_a[3] = V1_q_a[3]_PORT_A_data_out[0];


--A1L142 is rtl~0
--operation mode is normal

A1L142 = V1_q_a[4] & A1L145 & V1_q_a[2] & V1_q_a[3];


--N1_Q is chufa:inst21|Q
--operation mode is normal

N1_Q_lut_out = A1L129;
N1_Q = DFFEAS(N1_Q_lut_out, Fre17, VCC, , , , , , );


--S1_SUM[18] is add18:inst47|SUM[18]
--operation mode is normal

S1_SUM[18]_carry_eqn = S1L48;
S1_SUM[18]_lut_out = S1_SUM[18] $ (!S1_SUM[18]_carry_eqn);
S1_SUM[18] = DFFEAS(S1_SUM[18]_lut_out, K1_Cout, VCC, , S1L13, , , S1L51, );


--S1_SUM[8] is add18:inst47|SUM[8]
--operation mode is arithmetic

S1_SUM[8]_carry_eqn = S1L28;
S1_SUM[8]_lut_out = S1_SUM[8] $ (!S1_SUM[8]_carry_eqn);
S1_SUM[8] = DFFEAS(S1_SUM[8]_lut_out, K1_Cout, VCC, , S1L13, , , S1L51, );

--S1L30 is add18:inst47|SUM[8]~275
--operation mode is arithmetic

S1L30 = CARRY(S1_SUM[8] & (!S1L28));


--U2_q_b[7] is RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
U2_q_b[7]_PORT_A_data_in = in2[7];
U2_q_b[7]_PORT_A_data_in_reg = DFFE(U2_q_b[7]_PORT_A_data_in, U2_q_b[7]_clock_0, , , U2_q_b[7]_clock_enable_0);
U2_q_b[7]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U2_q_b[7]_PORT_A_address_reg = DFFE(U2_q_b[7]_PORT_A_address, U2_q_b[7]_clock_0, , , U2_q_b[7]_clock_enable_0);
U2_q_b[7]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U2_q_b[7]_PORT_B_address_reg = DFFE(U2_q_b[7]_PORT_B_address, U2_q_b[7]_clock_1, , , );
U2_q_b[7]_PORT_A_write_enable = VCC;
U2_q_b[7]_PORT_A_write_enable_reg = DFFE(U2_q_b[7]_PORT_A_write_enable, U2_q_b[7]_clock_0, , , U2_q_b[7]_clock_enable_0);
U2_q_b[7]_PORT_B_read_enable = inst36;
U2_q_b[7]_PORT_B_read_enable_reg = DFFE(U2_q_b[7]_PORT_B_read_enable, U2_q_b[7]_clock_1, , , );
U2_q_b[7]_clock_0 = CLK_40;
U2_q_b[7]_clock_1 = CLK_40;
U2_q_b[7]_clock_enable_0 = inst37;
U2_q_b[7]_PORT_B_data_out = MEMORY(U2_q_b[7]_PORT_A_data_in_reg, , U2_q_b[7]_PORT_A_address_reg, U2_q_b[7]_PORT_B_address_reg, U2_q_b[7]_PORT_A_write_enable_reg, U2_q_b[7]_PORT_B_read_enable_reg, , , U2_q_b[7]_clock_0, U2_q_b[7]_clock_1, U2_q_b[7]_clock_enable_0, , , );
U2_q_b[7]_PORT_B_data_out_reg = DFFE(U2_q_b[7]_PORT_B_data_out, U2_q_b[7]_clock_1, , , );
U2_q_b[7] = U2_q_b[7]_PORT_B_data_out_reg[0];


--U1_q_b[7] is RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
U1_q_b[7]_PORT_A_data_in = in1[7];
U1_q_b[7]_PORT_A_data_in_reg = DFFE(U1_q_b[7]_PORT_A_data_in, U1_q_b[7]_clock_0, , , U1_q_b[7]_clock_enable_0);
U1_q_b[7]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U1_q_b[7]_PORT_A_address_reg = DFFE(U1_q_b[7]_PORT_A_address, U1_q_b[7]_clock_0, , , U1_q_b[7]_clock_enable_0);
U1_q_b[7]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U1_q_b[7]_PORT_B_address_reg = DFFE(U1_q_b[7]_PORT_B_address, U1_q_b[7]_clock_1, , , );
U1_q_b[7]_PORT_A_write_enable = VCC;
U1_q_b[7]_PORT_A_write_enable_reg = DFFE(U1_q_b[7]_PORT_A_write_enable, U1_q_b[7]_clock_0, , , U1_q_b[7]_clock_enable_0);
U1_q_b[7]_PORT_B_read_enable = inst38;
U1_q_b[7]_PORT_B_read_enable_reg = DFFE(U1_q_b[7]_PORT_B_read_enable, U1_q_b[7]_clock_1, , , );
U1_q_b[7]_clock_0 = CLK_40;
U1_q_b[7]_clock_1 = CLK_40;
U1_q_b[7]_clock_enable_0 = inst37;
U1_q_b[7]_PORT_B_data_out = MEMORY(U1_q_b[7]_PORT_A_data_in_reg, , U1_q_b[7]_PORT_A_address_reg, U1_q_b[7]_PORT_B_address_reg, U1_q_b[7]_PORT_A_write_enable_reg, U1_q_b[7]_PORT_B_read_enable_reg, , , U1_q_b[7]_clock_0, U1_q_b[7]_clock_1, U1_q_b[7]_clock_enable_0, , , );
U1_q_b[7]_PORT_B_data_out_reg = DFFE(U1_q_b[7]_PORT_B_data_out, U1_q_b[7]_clock_1, , , );
U1_q_b[7] = U1_q_b[7]_PORT_B_data_out_reg[0];


--D1L15 is select2_1:inst31|out_q[7]~984
--operation mode is normal

D1L15 = A1L130 & U2_q_b[7] # !A1L130 & (U1_q_b[7]);


--L1_out_q[7] is select_q:inst19|out_q[7]
--operation mode is normal

L1_out_q[7]_lut_out = A1L130 & in2[7] # !A1L130 & (in1[7]);
L1_out_q[7] = DFFEAS(L1_out_q[7]_lut_out, K3_Cout, VCC, , , , , , );


--D1L16 is select2_1:inst31|out_q[7]~985
--operation mode is normal

D1L16 = A1L128 & D1L15 # !A1L128 & (L1_out_q[7]);


--U2_q_b[6] is RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
U2_q_b[6]_PORT_A_data_in = in2[6];
U2_q_b[6]_PORT_A_data_in_reg = DFFE(U2_q_b[6]_PORT_A_data_in, U2_q_b[6]_clock_0, , , U2_q_b[6]_clock_enable_0);
U2_q_b[6]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U2_q_b[6]_PORT_A_address_reg = DFFE(U2_q_b[6]_PORT_A_address, U2_q_b[6]_clock_0, , , U2_q_b[6]_clock_enable_0);
U2_q_b[6]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U2_q_b[6]_PORT_B_address_reg = DFFE(U2_q_b[6]_PORT_B_address, U2_q_b[6]_clock_1, , , );
U2_q_b[6]_PORT_A_write_enable = VCC;
U2_q_b[6]_PORT_A_write_enable_reg = DFFE(U2_q_b[6]_PORT_A_write_enable, U2_q_b[6]_clock_0, , , U2_q_b[6]_clock_enable_0);
U2_q_b[6]_PORT_B_read_enable = inst36;
U2_q_b[6]_PORT_B_read_enable_reg = DFFE(U2_q_b[6]_PORT_B_read_enable, U2_q_b[6]_clock_1, , , );
U2_q_b[6]_clock_0 = CLK_40;
U2_q_b[6]_clock_1 = CLK_40;
U2_q_b[6]_clock_enable_0 = inst37;
U2_q_b[6]_PORT_B_data_out = MEMORY(U2_q_b[6]_PORT_A_data_in_reg, , U2_q_b[6]_PORT_A_address_reg, U2_q_b[6]_PORT_B_address_reg, U2_q_b[6]_PORT_A_write_enable_reg, U2_q_b[6]_PORT_B_read_enable_reg, , , U2_q_b[6]_clock_0, U2_q_b[6]_clock_1, U2_q_b[6]_clock_enable_0, , , );
U2_q_b[6]_PORT_B_data_out_reg = DFFE(U2_q_b[6]_PORT_B_data_out, U2_q_b[6]_clock_1, , , );
U2_q_b[6] = U2_q_b[6]_PORT_B_data_out_reg[0];


--U1_q_b[6] is RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
U1_q_b[6]_PORT_A_data_in = in1[6];
U1_q_b[6]_PORT_A_data_in_reg = DFFE(U1_q_b[6]_PORT_A_data_in, U1_q_b[6]_clock_0, , , U1_q_b[6]_clock_enable_0);
U1_q_b[6]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U1_q_b[6]_PORT_A_address_reg = DFFE(U1_q_b[6]_PORT_A_address, U1_q_b[6]_clock_0, , , U1_q_b[6]_clock_enable_0);
U1_q_b[6]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U1_q_b[6]_PORT_B_address_reg = DFFE(U1_q_b[6]_PORT_B_address, U1_q_b[6]_clock_1, , , );
U1_q_b[6]_PORT_A_write_enable = VCC;
U1_q_b[6]_PORT_A_write_enable_reg = DFFE(U1_q_b[6]_PORT_A_write_enable, U1_q_b[6]_clock_0, , , U1_q_b[6]_clock_enable_0);
U1_q_b[6]_PORT_B_read_enable = inst38;
U1_q_b[6]_PORT_B_read_enable_reg = DFFE(U1_q_b[6]_PORT_B_read_enable, U1_q_b[6]_clock_1, , , );
U1_q_b[6]_clock_0 = CLK_40;
U1_q_b[6]_clock_1 = CLK_40;
U1_q_b[6]_clock_enable_0 = inst37;
U1_q_b[6]_PORT_B_data_out = MEMORY(U1_q_b[6]_PORT_A_data_in_reg, , U1_q_b[6]_PORT_A_address_reg, U1_q_b[6]_PORT_B_address_reg, U1_q_b[6]_PORT_A_write_enable_reg, U1_q_b[6]_PORT_B_read_enable_reg, , , U1_q_b[6]_clock_0, U1_q_b[6]_clock_1, U1_q_b[6]_clock_enable_0, , , );
U1_q_b[6]_PORT_B_data_out_reg = DFFE(U1_q_b[6]_PORT_B_data_out, U1_q_b[6]_clock_1, , , );
U1_q_b[6] = U1_q_b[6]_PORT_B_data_out_reg[0];


--D1L13 is select2_1:inst31|out_q[6]~986
--operation mode is normal

D1L13 = A1L130 & U2_q_b[6] # !A1L130 & (U1_q_b[6]);


--L1_out_q[6] is select_q:inst19|out_q[6]
--operation mode is normal

L1_out_q[6]_lut_out = A1L130 & in2[6] # !A1L130 & (in1[6]);
L1_out_q[6] = DFFEAS(L1_out_q[6]_lut_out, K3_Cout, VCC, , , , , , );


--D1L14 is select2_1:inst31|out_q[6]~987
--operation mode is normal

D1L14 = A1L128 & D1L13 # !A1L128 & (L1_out_q[6]);


--U2_q_b[5] is RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
U2_q_b[5]_PORT_A_data_in = in2[5];
U2_q_b[5]_PORT_A_data_in_reg = DFFE(U2_q_b[5]_PORT_A_data_in, U2_q_b[5]_clock_0, , , U2_q_b[5]_clock_enable_0);
U2_q_b[5]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U2_q_b[5]_PORT_A_address_reg = DFFE(U2_q_b[5]_PORT_A_address, U2_q_b[5]_clock_0, , , U2_q_b[5]_clock_enable_0);
U2_q_b[5]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U2_q_b[5]_PORT_B_address_reg = DFFE(U2_q_b[5]_PORT_B_address, U2_q_b[5]_clock_1, , , );
U2_q_b[5]_PORT_A_write_enable = VCC;
U2_q_b[5]_PORT_A_write_enable_reg = DFFE(U2_q_b[5]_PORT_A_write_enable, U2_q_b[5]_clock_0, , , U2_q_b[5]_clock_enable_0);
U2_q_b[5]_PORT_B_read_enable = inst36;
U2_q_b[5]_PORT_B_read_enable_reg = DFFE(U2_q_b[5]_PORT_B_read_enable, U2_q_b[5]_clock_1, , , );
U2_q_b[5]_clock_0 = CLK_40;
U2_q_b[5]_clock_1 = CLK_40;
U2_q_b[5]_clock_enable_0 = inst37;
U2_q_b[5]_PORT_B_data_out = MEMORY(U2_q_b[5]_PORT_A_data_in_reg, , U2_q_b[5]_PORT_A_address_reg, U2_q_b[5]_PORT_B_address_reg, U2_q_b[5]_PORT_A_write_enable_reg, U2_q_b[5]_PORT_B_read_enable_reg, , , U2_q_b[5]_clock_0, U2_q_b[5]_clock_1, U2_q_b[5]_clock_enable_0, , , );
U2_q_b[5]_PORT_B_data_out_reg = DFFE(U2_q_b[5]_PORT_B_data_out, U2_q_b[5]_clock_1, , , );
U2_q_b[5] = U2_q_b[5]_PORT_B_data_out_reg[0];


--U1_q_b[5] is RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
U1_q_b[5]_PORT_A_data_in = in1[5];
U1_q_b[5]_PORT_A_data_in_reg = DFFE(U1_q_b[5]_PORT_A_data_in, U1_q_b[5]_clock_0, , , U1_q_b[5]_clock_enable_0);
U1_q_b[5]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U1_q_b[5]_PORT_A_address_reg = DFFE(U1_q_b[5]_PORT_A_address, U1_q_b[5]_clock_0, , , U1_q_b[5]_clock_enable_0);
U1_q_b[5]_PORT_B_address = BUS(B1_Dout[0], B1_Dout[1], B1_Dout[2], B1_Dout[3], B1_Dout[4], B1_Dout[5], B1_Dout[6], B1_Dout[7], P2[0], P2[1]);
U1_q_b[5]_PORT_B_address_reg = DFFE(U1_q_b[5]_PORT_B_address, U1_q_b[5]_clock_1, , , );
U1_q_b[5]_PORT_A_write_enable = VCC;
U1_q_b[5]_PORT_A_write_enable_reg = DFFE(U1_q_b[5]_PORT_A_write_enable, U1_q_b[5]_clock_0, , , U1_q_b[5]_clock_enable_0);
U1_q_b[5]_PORT_B_read_enable = inst38;
U1_q_b[5]_PORT_B_read_enable_reg = DFFE(U1_q_b[5]_PORT_B_read_enable, U1_q_b[5]_clock_1, , , );
U1_q_b[5]_clock_0 = CLK_40;
U1_q_b[5]_clock_1 = CLK_40;
U1_q_b[5]_clock_enable_0 = inst37;
U1_q_b[5]_PORT_B_data_out = MEMORY(U1_q_b[5]_PORT_A_data_in_reg, , U1_q_b[5]_PORT_A_address_reg, U1_q_b[5]_PORT_B_address_reg, U1_q_b[5]_PORT_A_write_enable_reg, U1_q_b[5]_PORT_B_read_enable_reg, , , U1_q_b[5]_clock_0, U1_q_b[5]_clock_1, U1_q_b[5]_clock_enable_0, , , );
U1_q_b[5]_PORT_B_data_out_reg = DFFE(U1_q_b[5]_PORT_B_data_out, U1_q_b[5]_clock_1, , , );
U1_q_b[5] = U1_q_b[5]_PORT_B_data_out_reg[0];


--D1L11 is select2_1:inst31|out_q[5]~988
--operation mode is normal

D1L11 = A1L130 & U2_q_b[5] # !A1L130 & (U1_q_b[5]);


--L1_out_q[5] is select_q:inst19|out_q[5]
--operation mode is normal

L1_out_q[5]_lut_out = A1L130 & in2[5] # !A1L130 & (in1[5]);
L1_out_q[5] = DFFEAS(L1_out_q[5]_lut_out, K3_Cout, VCC, , , , , , );


--D1L12 is select2_1:inst31|out_q[5]~989
--operation mode is normal

D1L12 = A1L128 & D1L11 # !A1L128 & (L1_out_q[5]);


--U2_q_b[4] is RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
U2_q_b[4]_PORT_A_data_in = in2[4];
U2_q_b[4]_PORT_A_data_in_reg = DFFE(U2_q_b[4]_PORT_A_data_in, U2_q_b[4]_clock_0, , , U2_q_b[4]_clock_enable_0);
U2_q_b[4]_PORT_A_address = BUS(S1_SUM[8], S1_SUM[9], S1_SUM[10], S1_SUM[11], S1_SUM[12], S1_SUM[13], S1_SUM[14], S1_SUM[15], S1_SUM[16], S1_SUM[17]);
U2_q_b[4]_PORT_A_address_reg = DFFE(U2_q_b[4]_PORT_A_address, U2_q_b[4]_clock_0, , , U2_q_b[4]_clock_enable_0);