core_1c6.tan.rpt

运用TLC5510A高速(20M),扫描出波形,测量相位差,两个TLC5510A测两个波形.

Timing Analyzer report for core_1c6
Sun Dec 03 16:18:24 2006
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'ALE'
  6. Clock Setup: 'CLK_40'
  7. Clock Setup: 'Fre17'
  8. tsu
  9. tco
 10. tpd
 11. th
 12. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                              ;
+------------------------------+-------+---------------+------------------------------------------------+--------------------------+------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From                     ; To                                                                                                         ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+--------------------------+------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 11.045 ns                                      ; P2[7]                    ; RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|ram_block1a7~portb_re_reg     ; --         ; CLK_40   ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 24.136 ns                                      ; select_q:inst19|out_q[2] ; out0800[2]                                                                                                 ; CLK_40     ; --       ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 16.623 ns                                      ; P2[7]                    ; lcd_data[6]                                                                                                ; --         ; --       ; 0            ;