core_1c6.map.rpt

运用TLC5510A高速(20M),扫描出波形,测量相位差,两个TLC5510A测两个波形.

    Info: Found entity 1: Tlc5510
Warning: Can't analyze file -- file D:/Test_Phase/cexiang1/count.v is missing
Info: Found 1 design units, including 1 entities, in source file div_100.v
    Info: Found entity 1: div_100
Info: Found 1 design units, including 1 entities, in source file select2-1.v
    Info: Found entity 1: select2_1
Info: Found 1 design units, including 1 entities, in source file chufa.v
    Info: Found entity 1: chufa
Info: Found 1 design units, including 1 entities, in source file div_10.v
    Info: Found entity 1: div_10
Warning (10268): Verilog HDL information at ce_gao.v(24): Always Construct contains both blocking and non-blocking assignments
Warning (10261): Verilog HDL Event Control warning at ce_gao.v(31): Event Control contains a complex event expression
Info: Found 1 design units, including 1 entities, in source file ce_gao.v
    Info: Found entity 1: ce_gao
Info: Elaborating entity "core_1c6" for the top level hierarchy
Warning: Block or symbol "OR2" of instance "inst30" overlaps another block or symbol
Warning: Block or symbol "OR2" of instance "inst37" overlaps another block or symbol
Warning: Port "Din2" of type BUS_Connect and instance "inst9" is missing source signal
Warning: Port "Din5" of type BUS_Connect and instance "inst9" is missing source signal
Warning: Port "Din7" of type BUS_Connect and instance "inst9" is missing source signal
Info: Elaborating entity "Adr4_16" for hierarchy "Adr4_16:inst45"
Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(14): size of case item expression (32) exceeds the size of the case expression (4)
Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(15): size of case item expression (32) exceeds the size of the case expression (4)
Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(16): size of case item expression (32) exceeds the size of the case expression (4)
Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(17): size of case item expression (32) exceeds the size of the case expression (4)
Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(18): size of case item expression (32) exceeds the size of the case expression (4)
Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(19): size of case item expression (32) exceeds the size of the case expression (4)
Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(20): size of case item expression (32) exceeds the size of the case expression (4)
Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(21): size of case item expression (32) exceeds the size of the case expression (4)
Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(22): size of case item expression (32) exceeds the size of the case expression (4)
Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(23): size of case item expression (32) exceeds the size of the case expression (4)
Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(24): size of case item expression (32) exceeds the size of the case expression (4)
Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(25): size of case item expression (32) exceeds the size of the case expression (4)
Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(26): size of case item expression (32) exceeds the size of the case expression (4)
Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(27): size of case item expression (32) exceeds the size of the case expression (4)
Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(28): size of case item expression (32) exceeds the size of the case expression (4)
Warning (10271): Verilog HDL Case Statement warning at Adr4_16.v(29): size of case item expression (32) exceeds the size of the case expression (4)
Info: Elaborating entity "ScanKey" for hierarchy "ScanKey:inst15"
Warning (10230): Verilog HDL assignment warning at scankey.v(24): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at scankey.v(42): truncated value with size 32 to match size of target (3)
Info: Elaborating entity "chufa" for hierarchy "chufa:inst21"
Info: Elaborating entity "Tlc5510" for hierarchy "Tlc5510:inst20"
Info: Elaborating entity "add18" for hierarchy "add18:inst47"
Warning (10230): Verilog HDL assignment warning at add18.v(12): truncated value with size 11 to match size of target (10)
Info: Elaborating entity "fp_2" for hierarchy "fp_2:inst18"
Warning (10230): Verilog HDL assignment warning at fp_2.v(12): truncated value with size 32 to match size of target (1)
Info: Elaborating entity "data_ctl" for hierarchy "data_ctl:inst10"
Info: Elaborating entity "select2_1" for hierarchy "select2_1:inst31"
Warning: Using design file select_q.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: select_q
Info: Elaborating entity "select_q" for hierarchy "select_q:inst19"
Warning: Using design file RAM_1K.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: RAM_1K
Info: Elaborating entity "RAM_1K" for hierarchy "RAM_1K:inst5"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "RAM_1K:inst5|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_aqb1.tdf
    Info: Found entity 1: altsyncram_aqb1
Info: Elaborating entity "altsyncram_aqb1" for hierarchy "RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated"
Info: Elaborating entity "RAM_ADDR" for hierarchy "RAM_ADDR:inst13"
Info: Elaborating entity "ASIC74573" for hierarchy "ASIC74573:inst"
Info: Elaborating entity "BUS_Connect" for hierarchy "BUS_Connect:inst9"
Warning (10235): Verilog HDL Always Construct warning at bus_connect.v(17): variable "Din0" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at bus_connect.v(18): variable "Din1" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at bus_connect.v(19): variable "Din2" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at bus_connect.v(20): variable "Din3" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at bus_connect.v(21): variable "Din4" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at bus_connect.v(22): variable "Din5" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at bus_connect.v(23): variable "Din6" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at bus_connect.v(24): variable "Din7" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10270): Verilog HDL statement warning at bus_connect.v(16): incomplete Case Statement has no default case item
Warning (10240): Verilog HDL Always Construct warning at bus_connect.v(14): variable "Data_Temp" may not be assigned a new value in every possible path through the Always Construct.  Variable "Data_Temp" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Elaborating entity "ce_gao" for hierarchy "ce_gao:inst12"
Warning (10230): Verilog HDL assignment warning at ce_gao.v(29): truncated value with size 32 to match size of target (24)
Warning (10235): Verilog HDL Always Construct warning at ce_gao.v(33): variable "addr" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10271): Verilog HDL Case Statement warning at ce_gao.v(34): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10235): Verilog HDL Always Construct warning at ce_gao.v(34): variable "counter" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10271): Verilog HDL Case Statement warning at ce_gao.v(35): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10235): Verilog HDL Always Construct warning at ce_gao.v(35): variable "counter" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10271): Verilog HDL Case Statement warning at ce_gao.v(36): size of case item expression (32) exceeds the size of the case expression (2)
Warning (10235): Verilog HDL Always Construct warning at ce_gao.v(36): variable "counter" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Using design file div_1000.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: div_1000
Info: Elaborating entity "div_1000" for hierarchy "div_1000:inst33"
Warning (10230): Verilog HDL assignment warning at div_1000.v(13): truncated value with size 32 to match size of target (10)
Warning (10226): Verilog HDL Multiple Declaration warning at CONTER8.v(4): net, port, or variable "data_out" was previously declared without a range
Info (10007): Verilog HDL or VHDL information at CONTER8.v(3): data_out is declared here
Warning: Using design file CONTER8.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: CONTER8
Info: Elaborating entity "CONTER8" for hierarchy "CONTER8:inst35"
Warning (10230): Verilog HDL assignment warning at CONTER8.v(11): truncated value with size 32 to match size of target (10)
Warning: Reduced register "add18:inst47|DATA[17]" with stuck data_in port to stuck value GND
Warning: Reduced register "add18:inst47|DATA[16]" with stuck data_in port to stuck value GND
Warning: Reduced register "add18:inst47|DATA[15]" with stuck data_in port to stuck value GND
Warning: Reduced register "add18:inst47|DATA[14]" with stuck data_in port to stuck value GND
Warning: Reduced register "add18:inst47|DATA[13]" with stuck data_in port to stuck value GND
Warning: Reduced register "add18:inst47|DATA[12]" with stuck data_in port to stuck value GND
Warning: Reduced register "add18:inst47|DATA[11]" with stuck data_in port to stuck value GND
Warning: Reduced register "add18:inst47|DATA[10]" with stuck data_in port to stuck value GND
Warning: Reduced register "add18:inst47|DATA[9]" with stuck data_in port to stuck value GND
Warning: Reduced register "add18:inst47|DATA[8]" with stuck data_in port to stuck value GND
Warning: Reduced register "add18:inst47|DATA[18]" with stuck data_in port to stuck value GND
Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN
    Warning: Converting TRI node "ce_gao:inst12|data[7]" that feeds logic to a wire
    Warning: Converting TRI node "ce_gao:inst12|data[6]" that feeds logic to a wire
    Warning: Converting TRI node "ce_gao:inst12|data[5]" that feeds logic to a wire
    Warning: Converting TRI node "ce_gao:inst12|data[4]" that feeds logic to a wire
    Warning: Converting TRI node "ce_gao:inst12|data[3]" that feeds logic to a wire
    Warning: Converting TRI node "ce_gao:inst12|data[2]" that feeds logic to a wire
    Warning: Converting TRI node "ce_gao:inst12|data[1]" that feeds logic to a wire
    Warning: Converting TRI node "ce_gao:inst12|data[0]" that feeds logic to a wire
    Warning: Converting TRI node "ScanKey:inst15|Dout[7]" that feeds logic to a wire
    Warning: Converting TRI node "ScanKey:inst15|Dout[6]" that feeds logic to a wire
    Warning: Converting TRI node "ScanKey:inst15|Dout[5]" that feeds logic to a wire
    Warning: Converting TRI node "ScanKey:inst15|Dout[4]" that feeds logic to a wire
    Warning: Converting TRI node "ScanKey:inst15|Dout[3]" that feeds logic to a wire
    Warning: Converting TRI node "ScanKey:inst15|Dout[2]" that feeds logic to a wire
    Warning: Converting TRI node "ScanKey:inst15|Dout[1]" that feeds logic to a wire
    Warning: Converting TRI node "ScanKey:inst15|Dout[0]" that feeds logic to a wire
Info: Duplicate registers merged to single register
    Info: Duplicate register "ScanKey:inst15|KC_out[1]" merged to single register "ScanKey:inst15|KC_out[2]"
    Info: Duplicate register "ScanKey:inst15|KC_out[0]" merged to single register "ScanKey:inst15|KC_out[2]"
    Info: Duplicate register "ScanKey:inst15|KR_out[2]" merged to single register "ScanKey:inst15|KR_out[5]"
    Info: Duplicate register "ScanKey:inst15|KR_out[0]" merged to single register "ScanKey:inst15|KR_out[5]"
    Info: Duplicate register "ScanKey:inst15|KR_out[3]" merged to single register "ScanKey:inst15|KR_out[5]"
    Info: Duplicate register "ScanKey:inst15|KR_out[4]" merged to single register "ScanKey:inst15|KR_out[5]"
    Info: Du