jishu1-.vhd

MAX+plus II 9.23 Baseline

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity jishu1 is
port(clk1: in std_logic;
     ge1,shi1: inout std_logic_vector(3 downto 0);
     co_sec: out std_logic_vector(3 downto 0));
end jishu1;

architecture seconds of jishu1 is
signal ge,jin,jin1: std_logic_vector(3 downto 0);
begin
  process(clk1)
    begin
      if(clk1'event and clk1='1') then
         ge<=ge+1;
         ge1<=ge;
         if ge="1001" then
            jin<=jin+1;
            ge1<="0000";
            shi1<=jin;
            if shi1="0110" then
               jin1<=jin1+1;
               shi1<="0000";
            end if;  
         end if;
       end if;
  end process;
  co_sec<=jin1;
end;