kongzhi.vhd

MAX+plus II 9.23 Baseline

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity kongzhi is
port(clk: in std_logic;
     add: in std_logic;
     sel: in std_logic;
     co_sec,co_min: in std_logic;
     clk1,clk2,clk3: out std_logic);
end kongzhi;

architecture shijian of kongzhi is
   

begin


  process 
    variable sel1:std_logic_vector(1 downto 0):="00";
    begin
    if sel='0' then
           sel1:=sel1+1; 
    end if; 
    if sel1="00" then
          clk1<=clk; 
          clk2<=co_sec;
          clk3<=co_min;   
    elsif sel1="01" then
         clk1<=add;
    elsif sel1="10" then
         clk2<=add;
         clk1<='0'; 
    elsif sel1="11" then
         clk3<=add;
    end if;
  end process;
end shijian;