📄 jishu.rpt
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** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC23 co_sec
| +----------------------------- LC24 ge10
| | +--------------------------- LC30 ge11
| | | +------------------------- LC32 ge13
| | | | +----------------------- LC29 |LPM_ADD_SUB:87|addcore:adder|addcore:adder0|result_node1
| | | | | +--------------------- LC28 |LPM_ADD_SUB:87|addcore:adder|addcore:adder0|result_node2
| | | | | | +------------------- LC21 |LPM_ADD_SUB:87|addcore:adder|addcore:adder0|result_node3
| | | | | | | +----------------- LC17 shi10
| | | | | | | | +--------------- LC18 shi11
| | | | | | | | | +------------- LC19 shi12
| | | | | | | | | | +----------- LC20 shi13
| | | | | | | | | | | +--------- LC22 ge1~114
| | | | | | | | | | | | +------- LC25 shi3
| | | | | | | | | | | | | +----- LC26 shi2
| | | | | | | | | | | | | | +--- LC27 shi1~118
| | | | | | | | | | | | | | | +- LC31 shi0
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC29 -> * - - - - - - - * * - - - - - - | - * | <-- |LPM_ADD_SUB:87|addcore:adder|addcore:adder0|result_node1
LC28 -> * - - - - - - - * * - - - - - - | - * | <-- |LPM_ADD_SUB:87|addcore:adder|addcore:adder0|result_node2
LC21 -> * - - - - - - - * * * - * * * - | - * | <-- |LPM_ADD_SUB:87|addcore:adder|addcore:adder0|result_node3
LC17 -> - - - - - - - * - - - - - - - - | - * | <-- shi10
LC18 -> - - - - - - - - * - - - - - - - | - * | <-- shi11
LC19 -> - - - - - - - - - * - - - - - - | - * | <-- shi12
LC20 -> - - - - - - - - - - * - - - - - | - * | <-- shi13
LC25 -> - - - - - - * - - - - - * - - - | - * | <-- shi3
LC26 -> - - - - - * * - - - - - - * * - | - * | <-- shi2
LC27 -> - - - - * * * - - - - - - * * - | - * | <-- shi1~118
LC31 -> * - - - * * * * * * - - - * * * | - * | <-- shi0
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- clk1
LC8 -> * - * * - - - * * * * * * * * * | - * | <-- |LPM_ADD_SUB:63|addcore:adder|addcore:adder0|result_node1
LC12 -> * - * * - - - * * * * * * * * * | - * | <-- |LPM_ADD_SUB:63|addcore:adder|addcore:adder0|result_node2
LC4 -> * - * * - - - * * * * * * * * * | * * | <-- |LPM_ADD_SUB:63|addcore:adder|addcore:adder0|result_node3
LC5 -> * * * * - - - * * * * * * * * * | * * | <-- ge0~114
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\shuzizhong05\jishu.rpt
jishu
** EQUATIONS **
clk1 : INPUT;
-- Node name is 'co_sec' = 'jin'
-- Equation name is 'co_sec', location is LC023, type is output.
co_sec = DFFE( _EQ001 $ GND, GLOBAL( clk1), VCC, VCC, VCC);
_EQ001 = ge0~114 & _LC004 & _LC008 & !_LC012 & !_LC021 & _LC028 &
_LC029 & shi0;
-- Node name is ':32' = 'ge0~114'
-- Equation name is 'ge0~114', location is LC005, type is buried.
ge0~114 = TFFE( VCC, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':31' = 'ge1~114'
-- Equation name is 'ge1~114', location is LC022, type is buried.
ge1~114 = DFFE( _EQ002 $ _LC008, GLOBAL( clk1), VCC, VCC, VCC);
_EQ002 = ge0~114 & _LC004 & _LC008 & !_LC012;
-- Node name is ':30' = 'ge2~114'
-- Equation name is 'ge2~114', location is LC007, type is buried.
ge2~114 = TFFE( _EQ003, GLOBAL( clk1), VCC, VCC, VCC);
_EQ003 = ge0~114 & ge1~114;
-- Node name is ':29' = 'ge3~114'
-- Equation name is 'ge3~114', location is LC006, type is buried.
ge3~114 = DFFE( _EQ004 $ _LC004, GLOBAL( clk1), VCC, VCC, VCC);
_EQ004 = ge0~114 & !ge1~114 & !ge2~114 & _LC004;
-- Node name is 'ge10' = ':8'
-- Equation name is 'ge10', type is output
ge10 = DFFE( ge0~114 $ VCC, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is 'ge11' = ':6'
-- Equation name is 'ge11', type is output
ge11 = DFFE( _EQ005 $ _LC008, GLOBAL( clk1), VCC, VCC, VCC);
_EQ005 = ge0~114 & _LC004 & _LC008 & !_LC012;
-- Node name is 'ge12' = ':4'
-- Equation name is 'ge12', type is output
ge12 = DFFE( _EQ006 $ ge2~114, GLOBAL( clk1), VCC, VCC, VCC);
_EQ006 = ge0~114 & ge1~114;
-- Node name is 'ge13' = ':2'
-- Equation name is 'ge13', type is output
ge13 = DFFE( _EQ007 $ _LC004, GLOBAL( clk1), VCC, VCC, VCC);
_EQ007 = ge0~114 & _LC004 & _LC008 & !_LC012;
-- Node name is ':36' = 'shi0'
-- Equation name is 'shi0', location is LC031, type is buried.
shi0 = TFFE( _EQ008, GLOBAL( clk1), VCC, VCC, VCC);
_EQ008 = ge0~114 & _LC004 & _LC008 & !_LC012;
-- Node name is ':35' = 'shi1~118'
-- Equation name is 'shi1~118', location is LC027, type is buried.
shi1~118 = TFFE( _EQ009, GLOBAL( clk1), VCC, VCC, VCC);
_EQ009 = ge0~114 & _LC004 & _LC008 & !_LC012 & _LC021 & shi0 &
!shi1~118
# ge0~114 & _LC004 & _LC008 & !_LC012 & shi0 & !shi1~118 & !shi2
# ge0~114 & _LC004 & _LC008 & !_LC012 & shi0 & shi1~118;
-- Node name is ':34' = 'shi2'
-- Equation name is 'shi2', location is LC026, type is buried.
shi2 = TFFE( _EQ010, GLOBAL( clk1), VCC, VCC, VCC);
_EQ010 = ge0~114 & _LC004 & _LC008 & !_LC012 & !_LC021 & shi0 &
!shi1~118 & shi2
# ge0~114 & _LC004 & _LC008 & !_LC012 & shi0 & shi1~118;
-- Node name is ':33' = 'shi3'
-- Equation name is 'shi3', location is LC025, type is buried.
shi3 = TFFE( _EQ011, GLOBAL( clk1), VCC, VCC, VCC);
_EQ011 = ge0~114 & _LC004 & _LC008 & !_LC012 & _LC021 & !shi3
# ge0~114 & _LC004 & _LC008 & !_LC012 & !_LC021 & shi3;
-- Node name is 'shi10' = ':16'
-- Equation name is 'shi10', type is output
shi10 = TFFE( _EQ012, GLOBAL( clk1), VCC, VCC, VCC);
_EQ012 = ge0~114 & _LC004 & _LC008 & !_LC012 & shi0 & shi10
# ge0~114 & _LC004 & _LC008 & !_LC012 & !shi0 & !shi10;
-- Node name is 'shi11' = ':14'
-- Equation name is 'shi11', type is output
shi11 = TFFE( _EQ013, GLOBAL( clk1), VCC, VCC, VCC);
_EQ013 = ge0~114 & _LC004 & _LC008 & !_LC012 & !_LC021 & _LC028 & shi0 &
shi11
# ge0~114 & _LC004 & _LC008 & !_LC012 & _LC021 & _LC029 &
!shi11
# ge0~114 & _LC004 & _LC008 & !_LC012 & _LC029 & !shi0 & !shi11
# ge0~114 & _LC004 & _LC008 & !_LC012 & !_LC028 & _LC029 &
!shi11
# ge0~114 & _LC004 & _LC008 & !_LC012 & !_LC029 & shi11;
-- Node name is 'shi12' = ':12'
-- Equation name is 'shi12', type is output
shi12 = TFFE( _EQ014, GLOBAL( clk1), VCC, VCC, VCC);
_EQ014 = ge0~114 & _LC004 & _LC008 & !_LC012 & !_LC021 & _LC029 & shi0 &
shi12
# ge0~114 & _LC004 & _LC008 & !_LC012 & _LC021 & _LC028 &
!shi12
# ge0~114 & _LC004 & _LC008 & !_LC012 & _LC028 & !shi0 & !shi12
# ge0~114 & _LC004 & _LC008 & !_LC012 & _LC028 & !_LC029 &
!shi12
# ge0~114 & _LC004 & _LC008 & !_LC012 & !_LC028 & shi12;
-- Node name is 'shi13' = ':10'
-- Equation name is 'shi13', type is output
shi13 = TFFE( _EQ015, GLOBAL( clk1), VCC, VCC, VCC);
_EQ015 = ge0~114 & _LC004 & _LC008 & !_LC012 & _LC021 & !shi13
# ge0~114 & _LC004 & _LC008 & !_LC012 & !_LC021 & shi13;
-- Node name is '|LPM_ADD_SUB:63|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC008', type is buried
_LC008 = LCELL( ge1~114 $ ge0~114);
-- Node name is '|LPM_ADD_SUB:63|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC012', type is buried
_LC012 = LCELL( ge2~114 $ _EQ016);
_EQ016 = ge0~114 & ge1~114;
-- Node name is '|LPM_ADD_SUB:63|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC004', type is buried
_LC004 = LCELL( ge3~114 $ _EQ017);
_EQ017 = ge0~114 & ge1~114 & ge2~114;
-- Node name is '|LPM_ADD_SUB:87|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC029', type is buried
_LC029 = LCELL( shi1~118 $ shi0);
-- Node name is '|LPM_ADD_SUB:87|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC028', type is buried
_LC028 = LCELL( shi2 $ _EQ018);
_EQ018 = shi0 & shi1~118;
-- Node name is '|LPM_ADD_SUB:87|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC021', type is buried
_LC021 = LCELL( shi3 $ _EQ019);
_EQ019 = shi0 & shi1~118 & shi2;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\shuzizhong05\jishu.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,793K
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