kongzhi.rpt

MAX+plus II 9.23 Baseline

                             Logic cells placed in LAB 'B'
        +------------------- LC26 clk1
        | +----------------- LC17 clk2
        | | +--------------- LC18 clk3
        | | | +------------- LC25 |LPM_ADD_SUB:28|addcore:adder|addcore:adder0|result_node1
        | | | | +----------- LC24 ~38~1
        | | | | | +--------- LC23 ~44~1
        | | | | | | +------- LC22 ~106~1
        | | | | | | | +----- LC21 ~112~1
        | | | | | | | | +--- LC20 ~127~1~2
        | | | | | | | | | +- LC19 ~142~1~2
        | | | | | | | | | | 
        | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC17 -> - * - - - - - - * - | - * | <-- clk2
LC18 -> - - * - - - - - - * | - * | <-- clk3
LC25 -> - - - - * - - - - - | - * | <-- |LPM_ADD_SUB:28|addcore:adder|addcore:adder0|result_node1
LC24 -> * * * * * - * * * * | - * | <-- ~38~1
LC23 -> * * * * - * * * * * | - * | <-- ~44~1
LC22 -> - - - - - - - * - - | - * | <-- ~106~1
LC21 -> * - - - - - * * - - | - * | <-- ~112~1
LC20 -> - * - - - - - - - - | - * | <-- ~127~1~2
LC19 -> - - * - - - - - - - | - * | <-- ~142~1~2

Pin
4    -> * * * - - - * - * * | - * | <-- add
8    -> * - - - - - - * - - | - * | <-- clk
7    -> - - * - - - - - - - | - * | <-- co_min
6    -> - * - - - - - - * - | - * | <-- co_sec
5    -> - - - - * * - - - - | - * | <-- sel


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                       e:\shuzizhong05\kongzhi.rpt
kongzhi

** EQUATIONS **

add      : INPUT;
clk      : INPUT;
co_min   : INPUT;
co_sec   : INPUT;
sel      : INPUT;

-- Node name is 'clk1' 
-- Equation name is 'clk1', location is LC026, type is output.
 clk1    = LCELL( _EQ001 $  GND);
  _EQ001 =  _LC021 &  _LC023 &  _LC024 &  _X001
         #  add &  _LC023 & !_LC024 &  _X001
         #  _LC021 & !_LC023 & !_LC024 &  _X001
         #  clk & !_LC023 & !_LC024;
  _X001  = EXP(!_LC023 & !_LC024);

-- Node name is 'clk2' = '~127~1' 
-- Equation name is 'clk2', location is LC017, type is output.
 clk2    = LCELL( _EQ002 $  GND);
  _EQ002 =  add & !_LC023 &  _LC024 &  _X001
         #  clk2 &  _LC023 &  _X001
         #  clk2 & !_LC024 &  _X001
         #  co_sec & !_LC023 & !_LC024
         #  _LC020;
  _X001  = EXP(!_LC023 & !_LC024);

-- Node name is 'clk3' = '~142~1' 
-- Equation name is 'clk3', location is LC018, type is output.
 clk3    = LCELL( _EQ003 $  GND);
  _EQ003 =  add &  _LC023 &  _LC024 &  _X001
         #  clk3 & !_LC024 &  _X001
         #  clk3 & !_LC023 &  _X001
         #  co_min & !_LC023 & !_LC024
         #  _LC019;
  _X001  = EXP(!_LC023 & !_LC024);

-- Node name is '|LPM_ADD_SUB:28|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried 
_LC025   = LCELL( _LC024 $  _LC023);

-- Node name is '~38~1' 
-- Equation name is '~38~1', location is LC024, type is buried.
-- synthesized logic cell 
_LC024   = LCELL( _EQ004 $  GND);
  _EQ004 =  _LC024 &  sel
         #  _LC025 & !sel
         #  _LC024 &  _LC025;

-- Node name is '~44~1' 
-- Equation name is '~44~1', location is LC023, type is buried.
-- synthesized logic cell 
_LC023   = LCELL(!_LC023 $  sel);

-- Node name is '~106~1' 
-- Equation name is '~106~1', location is LC022, type is buried.
-- synthesized logic cell 
_LC022   = LCELL( _EQ005 $  GND);
  _EQ005 =  _LC021 &  _LC023 &  _LC024
         #  add &  _LC023 & !_LC024
         #  _LC021 & !_LC023 & !_LC024;

-- Node name is '~112~1' 
-- Equation name is '~112~1', location is LC021, type is buried.
-- synthesized logic cell 
_LC021   = LCELL( _EQ006 $  _LC022);
  _EQ006 =  clk & !_LC022 & !_LC023 & !_LC024
         # !clk &  _LC021 & !_LC023 & !_LC024
         #  _LC021 & !_LC022 & !_LC023 & !_LC024;

-- Node name is '~127~1~2' 
-- Equation name is '~127~1~2', location is LC020, type is buried.
-- synthesized logic cell 
_LC020   = LCELL( _EQ007 $  GND);
  _EQ007 =  add &  clk2 &  _LC024 &  _X001
         #  add &  clk2 & !_LC023 &  _X001
         #  add &  co_sec & !_LC023 &  _X001;
  _X001  = EXP(!_LC023 & !_LC024);

-- Node name is '~142~1~2' 
-- Equation name is '~142~1~2', location is LC019, type is buried.
-- synthesized logic cell 
_LC019   = LCELL( _EQ008 $  GND);
  _EQ008 =  add &  clk3 &  _LC023 &  _X001
         #  add &  clk3 &  _LC024 &  _X001;
  _X001  = EXP(!_LC023 & !_LC024);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                e:\shuzizhong05\kongzhi.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:01
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,751K