shuzizhong.rpt

MAX+plus II 9.23 Baseline

         #  _LC023 & !_LC028 & !_LC029;

-- Node name is '5' 
-- Equation name is '5', location is LC019, type is output.
 5       = LCELL( _EQ012 $ !_LC031);
  _EQ012 =  _LC023 &  _LC029 & !_LC031
         #  _LC028 & !_LC029 & !_LC031;

-- Node name is '6' 
-- Equation name is '6', location is LC024, type is output.
 6       = LCELL( _EQ013 $ !_LC029);
  _EQ013 = !_LC023 &  _LC028 &  _LC029 & !_LC031
         # !_LC023 & !_LC028 & !_LC029 &  _LC031
         #  _LC023 &  _LC028 & !_LC029;

-- Node name is '7' 
-- Equation name is '7', location is LC021, type is output.
 7       = LCELL( _EQ014 $ !_LC023);
  _EQ014 = !_LC023 &  _LC028 &  _LC029 &  _LC031
         # !_LC028 & !_LC029;

-- Node name is '8' = '|KONGZHI:70|~112~1' 
-- Equation name is '8', type is output 
 8       = LCELL( _EQ015 $  GND);
  _EQ015 =  _LC034 &  _LC048 &  8
         #  add & !_LC034 &  _LC048
         #  clk & !_LC034 & !_LC048
         #  add &  _LC048 &  8
         #  add &  clk & !_LC034;

-- Node name is '9' = '|KONGZHI:70|~127~1' 
-- Equation name is '9', type is output 
 9       = LCELL( _EQ016 $  GND);
  _EQ016 =  add &  _LC034 & !_LC048
         #  _LC032 & !_LC034 & !_LC048
         #  _LC048 &  9
         #  add &  _LC032 & !_LC048
         #  _LC055;

-- Node name is '|JISHU:7|:32' = '|JISHU:7|ge0~114' 
-- Equation name is '_LC049', type is buried 
_LC049   = TFFE( VCC,  8,  VCC,  VCC,  VCC);

-- Node name is '|JISHU:7|:31' = '|JISHU:7|ge1~114' 
-- Equation name is '_LC056', type is buried 
_LC056   = DFFE( _EQ017 $  _LC050,  8,  VCC,  VCC,  VCC);
  _EQ017 =  _LC049 &  _LC050 & !_LC059 &  _LC060;

-- Node name is '|JISHU:7|:30' = '|JISHU:7|ge2~114' 
-- Equation name is '_LC063', type is buried 
_LC063   = TFFE( _EQ018,  8,  VCC,  VCC,  VCC);
  _EQ018 =  _LC049 &  _LC056;

-- Node name is '|JISHU:7|:29' = '|JISHU:7|ge3~114' 
-- Equation name is '_LC061', type is buried 
_LC061   = DFFE( _EQ019 $  _LC060,  8,  VCC,  VCC,  VCC);
  _EQ019 =  _LC049 & !_LC056 &  _LC060 & !_LC063;

-- Node name is '|JISHU:7|:19' = '|JISHU:7|jin' 
-- Equation name is '_LC032', type is buried 
_LC032   = DFFE( _EQ020 $  GND,  8,  VCC,  VCC,  VCC);
  _EQ020 =  _LC040 & !_LC045 &  _LC047 &  _LC049 &  _LC050 &  _LC058 & 
             !_LC059 &  _LC060;

-- Node name is '|JISHU:7|LPM_ADD_SUB:63|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC050', type is buried 
_LC050   = LCELL( _LC056 $  _LC049);

-- Node name is '|JISHU:7|LPM_ADD_SUB:63|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC059', type is buried 
_LC059   = LCELL( _LC063 $  _EQ021);
  _EQ021 =  _LC049 &  _LC056;

-- Node name is '|JISHU:7|LPM_ADD_SUB:63|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC060', type is buried 
_LC060   = LCELL( _LC061 $  _EQ022);
  _EQ022 =  _LC049 &  _LC056 &  _LC063;

-- Node name is '|JISHU:7|LPM_ADD_SUB:87|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC040', type is buried 
_LC040   = LCELL( _LC026 $  _LC058);

-- Node name is '|JISHU:7|LPM_ADD_SUB:87|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC047', type is buried 
_LC047   = LCELL( _LC027 $  _EQ023);
  _EQ023 =  _LC026 &  _LC058;

-- Node name is '|JISHU:7|LPM_ADD_SUB:87|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC045', type is buried 
_LC045   = LCELL( _LC022 $  _EQ024);
  _EQ024 =  _LC026 &  _LC027 &  _LC058;

-- Node name is '|JISHU:7|:36' = '|JISHU:7|shi0' 
-- Equation name is '_LC058', type is buried 
_LC058   = TFFE( _EQ025,  8,  VCC,  VCC,  VCC);
  _EQ025 =  _LC049 &  _LC050 & !_LC059 &  _LC060;

-- Node name is '|JISHU:7|:35' = '|JISHU:7|shi1~118' 
-- Equation name is '_LC026', type is buried 
_LC026   = TFFE( _EQ026,  8,  VCC,  VCC,  VCC);
  _EQ026 = !_LC026 &  _LC045 &  _LC049 &  _LC050 &  _LC058 & !_LC059 & 
              _LC060
         # !_LC026 & !_LC027 &  _LC049 &  _LC050 &  _LC058 & !_LC059 & 
              _LC060
         #  _LC026 &  _LC049 &  _LC050 &  _LC058 & !_LC059 &  _LC060;

-- Node name is '|JISHU:7|:34' = '|JISHU:7|shi2' 
-- Equation name is '_LC027', type is buried 
_LC027   = TFFE( _EQ027,  8,  VCC,  VCC,  VCC);
  _EQ027 = !_LC026 &  _LC027 & !_LC045 &  _LC049 &  _LC050 &  _LC058 & 
             !_LC059 &  _LC060
         #  _LC026 &  _LC049 &  _LC050 &  _LC058 & !_LC059 &  _LC060;

-- Node name is '|JISHU:7|:33' = '|JISHU:7|shi3' 
-- Equation name is '_LC022', type is buried 
_LC022   = TFFE( _EQ028,  8,  VCC,  VCC,  VCC);
  _EQ028 = !_LC022 &  _LC045 &  _LC049 &  _LC050 & !_LC059 &  _LC060
         #  _LC022 & !_LC045 &  _LC049 &  _LC050 & !_LC059 &  _LC060;

-- Node name is '|JISHU:7|:2' 
-- Equation name is '_LC052', type is buried 
_LC052   = DFFE( _EQ029 $  _LC060,  _EQ030,  VCC,  VCC,  VCC);
  _EQ029 =  _LC049 &  _LC050 & !_LC059 &  _LC060;
  _EQ030 =  _X001 &  _X002;
  _X001  = EXP(!clk & !_LC034 & !_LC048);
  _X002  = EXP(!_LC043 & !_LC054);

-- Node name is '|JISHU:7|:4' 
-- Equation name is '_LC051', type is buried 
_LC051   = DFFE( _EQ031 $  _LC063,  8,  VCC,  VCC,  VCC);
  _EQ031 =  _LC049 &  _LC056;

-- Node name is '|JISHU:7|:6' 
-- Equation name is '_LC018', type is buried 
_LC018   = DFFE( _EQ032 $  _LC050,  8,  VCC,  VCC,  VCC);
  _EQ032 =  _LC049 &  _LC050 & !_LC059 &  _LC060;

-- Node name is '|JISHU:7|:8' 
-- Equation name is '_LC057', type is buried 
_LC057   = DFFE( _LC049 $  VCC,  8,  VCC,  VCC,  VCC);

-- Node name is '|JISHU:7|:10' 
-- Equation name is '_LC023', type is buried 
_LC023   = TFFE( _EQ033,  8,  VCC,  VCC,  VCC);
  _EQ033 = !_LC023 &  _LC045 &  _LC049 &  _LC050 & !_LC059 &  _LC060
         #  _LC023 & !_LC045 &  _LC049 &  _LC050 & !_LC059 &  _LC060;

-- Node name is '|JISHU:7|:12' 
-- Equation name is '_LC028', type is buried 
_LC028   = TFFE( _EQ034,  8,  VCC,  VCC,  VCC);
  _EQ034 =  _LC028 &  _LC040 & !_LC045 &  _LC049 &  _LC050 &  _LC058 & 
             !_LC059 &  _LC060
         # !_LC028 &  _LC047 &  _LC049 &  _LC050 & !_LC059 &  _LC060 &  _X003
         #  _LC028 & !_LC047 &  _LC049 &  _LC050 & !_LC059 &  _LC060;
  _X003  = EXP( _LC040 & !_LC045 &  _LC058);

-- Node name is '|JISHU:7|:14' 
-- Equation name is '_LC029', type is buried 
_LC029   = TFFE( _EQ035,  8,  VCC,  VCC,  VCC);
  _EQ035 =  _LC029 & !_LC045 &  _LC047 &  _LC049 &  _LC050 &  _LC058 & 
             !_LC059 &  _LC060
         # !_LC029 &  _LC040 &  _LC049 &  _LC050 & !_LC059 &  _LC060 &  _X004
         #  _LC029 & !_LC040 &  _LC049 &  _LC050 & !_LC059 &  _LC060;
  _X004  = EXP(!_LC045 &  _LC047 &  _LC058);

-- Node name is '|JISHU:7|:16' 
-- Equation name is '_LC031', type is buried 
_LC031   = TFFE( _EQ036,  8,  VCC,  VCC,  VCC);
  _EQ036 =  _LC031 &  _LC049 &  _LC050 &  _LC058 & !_LC059 &  _LC060
         # !_LC031 &  _LC049 &  _LC050 & !_LC058 & !_LC059 &  _LC060;

-- Node name is '|KONGZHI:70|LPM_ADD_SUB:28|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC053', type is buried 
_LC053   = LCELL( _LC034 $  _LC048);

-- Node name is '|KONGZHI:70|~38~1' 
-- Equation name is '_LC034', type is buried 
-- synthesized logic cell 
_LC034   = LCELL( _EQ037 $  GND);
  _EQ037 =  _LC034 &  sel1
         #  _LC053 & !sel1
         #  _LC034 &  _LC053;

-- Node name is '|KONGZHI:70|~44~1' 
-- Equation name is '_LC048', type is buried 
-- synthesized logic cell 
_LC048   = LCELL(!_LC048 $  sel1);

-- Node name is '|KONGZHI:70|~106~1' 
-- Equation name is '_LC054', type is buried 
-- synthesized logic cell 
_LC054   = LCELL( _EQ038 $  GND);
  _EQ038 =  _LC034 &  _LC048 &  8
         #  add & !_LC034 &  _LC048
         # !_LC034 & !_LC048 &  8;

-- Node name is '|KONGZHI:70|~110~1' 
-- Equation name is '_LC043', type is buried 
-- synthesized logic cell 
_LC043   = LCELL( _EQ039 $  GND);
  _EQ039 = !_LC034 & !_LC048;

-- Node name is '|KONGZHI:70|~127~1~2' 
-- Equation name is '_LC055', type is buried 
-- synthesized logic cell 
_LC055   = LCELL( _EQ040 $  GND);
  _EQ040 =  add &  _LC034 &  9
         #  _LC032 & !_LC034 &  9;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                             e:\shuzizhong05\shuzizhong.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 7,045K