📄 shuzizhong.rpt
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Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 50 D SOFT t 0 0 0 0 2 0 12 |JISHU:7|LPM_ADD_SUB:63|addcore:adder|addcore:adder0|result_node1
- 59 D SOFT t 0 0 0 0 3 0 12 |JISHU:7|LPM_ADD_SUB:63|addcore:adder|addcore:adder0|result_node2
- 60 D SOFT t 0 0 0 0 4 0 13 |JISHU:7|LPM_ADD_SUB:63|addcore:adder|addcore:adder0|result_node3
(28) 40 C SOFT t 0 0 0 0 2 0 3 |JISHU:7|LPM_ADD_SUB:87|addcore:adder|addcore:adder0|result_node1
- 47 C SOFT t 0 0 0 0 3 0 3 |JISHU:7|LPM_ADD_SUB:87|addcore:adder|addcore:adder0|result_node2
- 45 C SOFT t 0 0 0 0 4 0 7 |JISHU:7|LPM_ADD_SUB:87|addcore:adder|addcore:adder0|result_node3
(36) 52 D DFFE t 2 0 0 1 8 7 0 |JISHU:7|:2
(34) 51 D DFFE t 0 0 0 0 4 7 0 |JISHU:7|:4
- 18 B DFFE t 0 0 0 0 5 7 0 |JISHU:7|:6
(39) 57 D DFFE t 0 0 0 0 2 7 0 |JISHU:7|:8
- 23 B TFFE t 0 0 0 0 7 7 1 |JISHU:7|:10
- 28 B TFFE t 1 0 0 0 10 7 1 |JISHU:7|:12
- 29 B TFFE t 1 0 0 0 10 7 1 |JISHU:7|:14
- 31 B TFFE t 0 0 0 0 7 7 1 |JISHU:7|:16
(13) 32 B DFFE t 0 0 0 0 9 1 1 |JISHU:7|jin (|JISHU:7|:19)
- 61 D DFFE t 0 0 0 0 5 0 1 |JISHU:7|ge3~114 (|JISHU:7|:29)
- 63 D TFFE t 0 0 0 0 3 0 4 |JISHU:7|ge2~114 (|JISHU:7|:30)
(38) 56 D DFFE t 0 0 0 0 5 0 6 |JISHU:7|ge1~114 (|JISHU:7|:31)
(33) 49 D TFFE t 0 0 0 0 1 0 19 |JISHU:7|ge0~114 (|JISHU:7|:32)
- 22 B TFFE t 0 0 0 0 7 0 2 |JISHU:7|shi3 (|JISHU:7|:33)
- 27 B TFFE t 0 0 0 0 9 0 4 |JISHU:7|shi2 (|JISHU:7|:34)
- 26 B TFFE t 0 0 0 0 9 0 5 |JISHU:7|shi1~118 (|JISHU:7|:35)
- 58 D TFFE t 0 0 0 0 5 0 9 |JISHU:7|shi0 (|JISHU:7|:36)
(37) 53 D SOFT t 0 0 0 0 2 0 1 |KONGZHI:70|LPM_ADD_SUB:28|addcore:adder|addcore:adder0|result_node1
- 34 C LCELL s t 0 0 0 1 2 2 6 |KONGZHI:70|~38~1
(32) 48 C LCELL s t 0 0 0 1 1 2 5 |KONGZHI:70|~44~1
- 54 D SOFT s t 0 0 0 1 3 0 1 |KONGZHI:70|~106~1
- 43 C SOFT s t 0 0 0 0 2 0 1 |KONGZHI:70|~110~1
- 55 D LCELL s t 0 0 0 1 3 1 0 |KONGZHI:70|~127~1~2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\shuzizhong05\shuzizhong.rpt
shuzizhong
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----- LC5 d
| +--- LC4 e
| | +- LC1 3
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'A'
LC | | | | A B C D | Logic cells that feed LAB 'A':
Pin
43 -> - - - | - - - * | <-- clk
LC52 -> * * - | * * * - | <-- |JISHU:7|:2
LC51 -> * * - | * * * - | <-- |JISHU:7|:4
LC18 -> * * - | * * * - | <-- |JISHU:7|:6
LC57 -> * * - | * * * - | <-- |JISHU:7|:8
LC23 -> - - * | * * - - | <-- |JISHU:7|:10
LC28 -> - - * | * * - - | <-- |JISHU:7|:12
LC29 -> - - * | * * - - | <-- |JISHU:7|:14
LC31 -> - - * | * * - - | <-- |JISHU:7|:16
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\shuzizhong05\shuzizhong.rpt
shuzizhong
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC17 g
| +----------------------------- LC18 |JISHU:7|:6
| | +--------------------------- LC23 |JISHU:7|:10
| | | +------------------------- LC28 |JISHU:7|:12
| | | | +----------------------- LC29 |JISHU:7|:14
| | | | | +--------------------- LC31 |JISHU:7|:16
| | | | | | +------------------- LC32 |JISHU:7|jin
| | | | | | | +----------------- LC22 |JISHU:7|shi3
| | | | | | | | +--------------- LC27 |JISHU:7|shi2
| | | | | | | | | +------------- LC26 |JISHU:7|shi1~118
| | | | | | | | | | +----------- LC25 1
| | | | | | | | | | | +--------- LC30 2
| | | | | | | | | | | | +------- LC20 4
| | | | | | | | | | | | | +----- LC19 5
| | | | | | | | | | | | | | +--- LC24 6
| | | | | | | | | | | | | | | +- LC21 7
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'B':
LC18 -> * - - - - - - - - - - - - - - - | * * * - | <-- |JISHU:7|:6
LC23 -> - - * - - - - - - - * * * * * * | * * - - | <-- |JISHU:7|:10
LC28 -> - - - * - - - - - - * * * * * * | * * - - | <-- |JISHU:7|:12
LC29 -> - - - - * - - - - - * * * * * * | * * - - | <-- |JISHU:7|:14
LC31 -> - - - - - * - - - - * * * * * * | * * - - | <-- |JISHU:7|:16
LC22 -> - - - - - - - * - - - - - - - - | - * * - | <-- |JISHU:7|shi3
LC27 -> - - - - - - - - * * - - - - - - | - * * - | <-- |JISHU:7|shi2
LC26 -> - - - - - - - - * * - - - - - - | - * * - | <-- |JISHU:7|shi1~118
Pin
43 -> - - - - - - - - - - - - - - - - | - - - * | <-- clk
LC50 -> - * * * * * * * * * - - - - - - | - * - * | <-- |JISHU:7|LPM_ADD_SUB:63|addcore:adder|addcore:adder0|result_node1
LC59 -> - * * * * * * * * * - - - - - - | - * - * | <-- |JISHU:7|LPM_ADD_SUB:63|addcore:adder|addcore:adder0|result_node2
LC60 -> - * * * * * * * * * - - - - - - | - * - * | <-- |JISHU:7|LPM_ADD_SUB:63|addcore:adder|addcore:adder0|result_node3
LC40 -> - - - * * - * - - - - - - - - - | - * - - | <-- |JISHU:7|LPM_ADD_SUB:87|addcore:adder|addcore:adder0|result_node1
LC47 -> - - - * * - * - - - - - - - - - | - * - - | <-- |JISHU:7|LPM_ADD_SUB:87|addcore:adder|addcore:adder0|result_node2
LC45 -> - - * * * - * * * * - - - - - - | - * - - | <-- |JISHU:7|LPM_ADD_SUB:87|addcore:adder|addcore:adder0|result_node3
LC52 -> * - - - - - - - - - - - - - - - | * * * - | <-- |JISHU:7|:2
LC51 -> * - - - - - - - - - - - - - - - | * * * - | <-- |JISHU:7|:4
LC57 -> * - - - - - - - - - - - - - - - | * * * - | <-- |JISHU:7|:8
LC49 -> - * * * * * * * * * - - - - - - | - * - * | <-- |JISHU:7|ge0~114
LC58 -> - - - * * * * - * * - - - - - - | - * * - | <-- |JISHU:7|shi0
LC62 -> - * * * * * * * * * - - - - - - | - * - * | <-- 8
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\shuzizhong05\shuzizhong.rpt
shuzizhong
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------- LC35 a
| +----------------- LC36 b
| | +--------------- LC37 c
| | | +------------- LC33 f
| | | | +----------- LC40 |JISHU:7|LPM_ADD_SUB:87|addcore:adder|addcore:adder0|result_node1
| | | | | +--------- LC47 |JISHU:7|LPM_ADD_SUB:87|addcore:adder|addcore:adder0|result_node2
| | | | | | +------- LC45 |JISHU:7|LPM_ADD_SUB:87|addcore:adder|addcore:adder0|result_node3
| | | | | | | +----- LC34 |KONGZHI:70|~38~1
| | | | | | | | +--- LC48 |KONGZHI:70|~44~1
| | | | | | | | | +- LC43 |KONGZHI:70|~110~1
| | | | | | | | | |
| | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC34 -> - - - - - - - * - * | - - * * | <-- |KONGZHI:70|~38~1
LC48 -> - - - - - - - - * * | - - * * | <-- |KONGZHI:70|~44~1
Pin
43 -> - - - - - - - - - - | - - - * | <-- clk
4 -> - - - - - - - * * - | - - * - | <-- sel1
LC52 -> * * * * - - - - - - | * * * - | <-- |JISHU:7|:2
LC51 -> * * * * - - - - - - | * * * - | <-- |JISHU:7|:4
LC18 -> * * * * - - - - - - | * * * - | <-- |JISHU:7|:6
LC57 -> * * * * - - - - - - | * * * - | <-- |JISHU:7|:8
LC22 -> - - - - - - * - - - | - * * - | <-- |JISHU:7|shi3
LC27 -> - - - - - * * - - - | - * * - | <-- |JISHU:7|shi2
LC26 -> - - - - * * * - - - | - * * - | <-- |JISHU:7|shi1~118
LC58 -> - - - - * * * - - - | - * * - | <-- |JISHU:7|shi0
LC53 -> - - - - - - - * - - | - - * - | <-- |KONGZHI:70|LPM_ADD_SUB:28|addcore:adder|addcore:adder0|result_node1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\shuzizhong05\shuzizhong.rpt
shuzizhong
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC50 |JISHU:7|LPM_ADD_SUB:63|addcore:adder|addcore:adder0|result_node1
| +----------------------------- LC59 |JISHU:7|LPM_ADD_SUB:63|addcore:adder|addcore:adder0|result_node2
| | +--------------------------- LC60 |JISHU:7|LPM_ADD_SUB:63|addcore:adder|addcore:adder0|result_node3
| | | +------------------------- LC52 |JISHU:7|:2
| | | | +----------------------- LC51 |JISHU:7|:4
| | | | | +--------------------- LC57 |JISHU:7|:8
| | | | | | +------------------- LC61 |JISHU:7|ge3~114
| | | | | | | +----------------- LC63 |JISHU:7|ge2~114
| | | | | | | | +--------------- LC56 |JISHU:7|ge1~114
| | | | | | | | | +------------- LC49 |JISHU:7|ge0~114
| | | | | | | | | | +----------- LC58 |JISHU:7|shi0
| | | | | | | | | | | +--------- LC53 |KONGZHI:70|LPM_ADD_SUB:28|addcore:adder|addcore:adder0|result_node1
| | | | | | | | | | | | +------- LC54 |KONGZHI:70|~106~1
| | | | | | | | | | | | | +----- LC55 |KONGZHI:70|~127~1~2
| | | | | | | | | | | | | | +--- LC62 8
| | | | | | | | | | | | | | | +- LC64 9
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC50 -> - - - * - - - - * - * - - - - - | - * - * | <-- |JISHU:7|LPM_ADD_SUB:63|addcore:adder|addcore:adder0|result_node1
LC59 -> - - - * - - - - * - * - - - - - | - * - * | <-- |JISHU:7|LPM_ADD_SUB:63|addcore:adder|addcore:adder0|result_node2
LC60 -> - - - * - - * - * - * - - - - - | - * - * | <-- |JISHU:7|LPM_ADD_SUB:63|addcore:adder|addcore:adder0|result_node3
LC61 -> - - * - - - - - - - - - - - - - | - - - * | <-- |JISHU:7|ge3~114
LC63 -> - * * - * - * * - - - - - - - - | - - - * | <-- |JISHU:7|ge2~114
LC56 -> * * * - * - * * - - - - - - - - | - - - * | <-- |JISHU:7|ge1~114
LC49 -> * * * * * * * * * * * - - - - - | - * - * | <-- |JISHU:7|ge0~114
LC54 -> - - - * - - - - - - - - - - - - | - - - * | <-- |KONGZHI:70|~106~1
LC55 -> - - - - - - - - - - - - - - - * | - - - * | <-- |KONGZHI:70|~127~1~2
LC62 -> - - - - * * * * * * * - * - * - | - * - * | <-- 8
LC64 -> - - - - - - - - - - - - - * - * | - - - * | <-- 9
Pin
5 -> - - - - - - - - - - - - * * * * | - - - * | <-- add
43 -> - - - * - - - - - - - - - - * - | - - - * | <-- clk
LC32 -> - - - - - - - - - - - - - * - * | - - - * | <-- |JISHU:7|jin
LC34 -> - - - * - - - - - - - * * * * * | - - * * | <-- |KONGZHI:70|~38~1
LC48 -> - - - * - - - - - - - * * - * * | - - * * | <-- |KONGZHI:70|~44~1
LC43 -> - - - * - - - - - - - - - - - - | - - - * | <-- |KONGZHI:70|~110~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\shuzizhong05\shuzizhong.rpt
shuzizhong
** EQUATIONS **
add : INPUT;
clk : INPUT;
sel1 : INPUT;
-- Node name is 'a'
-- Equation name is 'a', location is LC035, type is output.
a = LCELL( _EQ001 $ !_LC052);
_EQ001 = !_LC018 & !_LC051 & !_LC052 & _LC057
# !_LC018 & _LC051 & !_LC052 & !_LC057
# !_LC018 & !_LC051 & _LC052;
-- Node name is 'b'
-- Equation name is 'b', location is LC036, type is output.
b = LCELL( _EQ002 $ !_LC052);
_EQ002 = !_LC018 & _LC051 & !_LC052 & _LC057
# _LC018 & _LC051 & !_LC052 & !_LC057
# !_LC018 & !_LC051 & _LC052;
-- Node name is 'c'
-- Equation name is 'c', location is LC037, type is output.
c = LCELL( _EQ003 $ !_LC052);
_EQ003 = _LC018 & !_LC051 & !_LC052 & !_LC057
# !_LC018 & !_LC051 & _LC052;
-- Node name is 'd'
-- Equation name is 'd', location is LC005, type is output.
d = LCELL( _EQ004 $ !_LC052);
_EQ004 = _LC018 & _LC051 & !_LC052 & _LC057
# !_LC018 & !_LC051 & !_LC052 & _LC057
# !_LC018 & _LC051 & !_LC052 & !_LC057
# !_LC018 & !_LC051 & _LC052;
-- Node name is 'e'
-- Equation name is 'e', location is LC004, type is output.
e = LCELL( _EQ005 $ !_LC057);
_EQ005 = _LC018 & _LC052 & !_LC057
# !_LC018 & _LC051 & !_LC057;
-- Node name is 'f'
-- Equation name is 'f', location is LC033, type is output.
f = LCELL( _EQ006 $ !_LC018);
_EQ006 = _LC018 & _LC051 & !_LC052 & !_LC057
# !_LC018 & !_LC051 & !_LC052 & _LC057
# !_LC018 & _LC051 & _LC052;
-- Node name is 'g'
-- Equation name is 'g', location is LC017, type is output.
g = LCELL( _EQ007 $ !_LC052);
_EQ007 = _LC018 & _LC051 & !_LC052 & _LC057
# !_LC018 & !_LC051;
-- Node name is '1'
-- Equation name is '1', location is LC025, type is output.
1 = LCELL( _EQ008 $ !_LC023);
_EQ008 = !_LC023 & !_LC028 & !_LC029 & _LC031
# !_LC023 & _LC028 & !_LC029 & !_LC031
# _LC023 & !_LC028 & !_LC029;
-- Node name is '2'
-- Equation name is '2', location is LC030, type is output.
2 = LCELL( _EQ009 $ !_LC023);
_EQ009 = !_LC023 & _LC028 & !_LC029 & _LC031
# !_LC023 & _LC028 & _LC029 & !_LC031
# _LC023 & !_LC028 & !_LC029;
-- Node name is '3'
-- Equation name is '3', location is LC001, type is output.
3 = LCELL( _EQ010 $ !_LC023);
_EQ010 = !_LC023 & !_LC028 & _LC029 & !_LC031
# _LC023 & !_LC028 & !_LC029;
-- Node name is '4'
-- Equation name is '4', location is LC020, type is output.
4 = LCELL( _EQ011 $ !_LC023);
_EQ011 = !_LC023 & _LC028 & _LC029 & _LC031
# !_LC023 & !_LC028 & !_LC029 & _LC031
# !_LC023 & _LC028 & !_LC029 & !_LC031
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