📄 jishu2.rpt
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jishu2
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC24 ge11
| +----------------------------- LC23 ge12
| | +--------------------------- LC22 ge13
| | | +------------------------- LC26 |LPM_ADD_SUB:91|addcore:adder|addcore:adder0|result_node1
| | | | +----------------------- LC21 |LPM_ADD_SUB:91|addcore:adder|addcore:adder0|result_node2
| | | | | +--------------------- LC25 |LPM_ADD_SUB:91|addcore:adder|addcore:adder0|result_node3
| | | | | | +------------------- LC20 shi10
| | | | | | | +----------------- LC19 shi11
| | | | | | | | +--------------- LC18 shi12
| | | | | | | | | +------------- LC17 shi13
| | | | | | | | | | +----------- LC32 ge2~105
| | | | | | | | | | | +--------- LC31 ge1~105
| | | | | | | | | | | | +------- LC30 shi3
| | | | | | | | | | | | | +----- LC29 shi2
| | | | | | | | | | | | | | +--- LC28 shi1~109
| | | | | | | | | | | | | | | +- LC27 shi0
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC26 -> - - - - - - - * - - - - - - - - | - * | <-- |LPM_ADD_SUB:91|addcore:adder|addcore:adder0|result_node1
LC21 -> - - - - - - - - * - - - - - - - | - * | <-- |LPM_ADD_SUB:91|addcore:adder|addcore:adder0|result_node2
LC25 -> - - - - - - - - - * - - - - - - | - * | <-- |LPM_ADD_SUB:91|addcore:adder|addcore:adder0|result_node3
LC20 -> - - - - - - * - - - - - - - - - | - * | <-- shi10
LC19 -> - - - - - - - * - - - - - - - - | - * | <-- shi11
LC18 -> - - - - - - - - * - - - - - - - | - * | <-- shi12
LC17 -> - - - - - - - - - * - - - - - - | - * | <-- shi13
LC30 -> - * - - - * * * * * * - * - * - | - * | <-- shi3
LC29 -> - * - - * * * * * * * - * * * - | - * | <-- shi2
LC28 -> - * - * * * * * * * * - * * * - | - * | <-- shi1~109
LC27 -> - * - * * * * * * * * - * * * * | - * | <-- shi0
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- clk1
LC7 -> * * * - - - * * * * * * * * * * | - * | <-- |LPM_ADD_SUB:62|addcore:adder|addcore:adder0|result_node1
LC6 -> * * * - - - * * * * * * * * * * | - * | <-- |LPM_ADD_SUB:62|addcore:adder|addcore:adder0|result_node2
LC4 -> * * * - - - * * * * * * * * * * | * * | <-- |LPM_ADD_SUB:62|addcore:adder|addcore:adder0|result_node3
LC5 -> * * * - - - * * * * * * * * * * | * * | <-- ge0~105
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\shuzizhong05\jishu2.rpt
jishu2
** EQUATIONS **
clk1 : INPUT;
-- Node name is ':29' = 'ge0~105'
-- Equation name is 'ge0~105', location is LC005, type is buried.
ge0~105 = TFFE( VCC, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':28' = 'ge1~105'
-- Equation name is 'ge1~105', location is LC031, type is buried.
ge1~105 = DFFE( _EQ001 $ _LC007, GLOBAL( clk1), VCC, VCC, VCC);
_EQ001 = ge0~105 & _LC004 & !_LC006 & _LC007;
-- Node name is ':27' = 'ge2~105'
-- Equation name is 'ge2~105', location is LC032, type is buried.
ge2~105 = DFFE( _EQ002 $ _LC006, GLOBAL( clk1), VCC, VCC, VCC);
_EQ002 = ge0~105 & !_LC004 & _LC006 & !_LC007 & !shi0 & shi1~109 & !shi2 &
!shi3;
-- Node name is ':26' = 'ge3~105'
-- Equation name is 'ge3~105', location is LC008, type is buried.
ge3~105 = DFFE( _EQ003 $ _LC004, GLOBAL( clk1), VCC, VCC, VCC);
_EQ003 = ge0~105 & !ge1~105 & !ge2~105 & _LC004;
-- Node name is 'ge10' = ':8'
-- Equation name is 'ge10', type is output
ge10 = DFFE( ge0~105 $ VCC, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is 'ge11' = ':6'
-- Equation name is 'ge11', type is output
ge11 = DFFE( _EQ004 $ _LC007, GLOBAL( clk1), VCC, VCC, VCC);
_EQ004 = ge0~105 & _LC004 & !_LC006 & _LC007;
-- Node name is 'ge12' = ':4'
-- Equation name is 'ge12', type is output
ge12 = DFFE( _EQ005 $ _LC006, GLOBAL( clk1), VCC, VCC, VCC);
_EQ005 = ge0~105 & !_LC004 & _LC006 & !_LC007 & !shi0 & shi1~109 & !shi2 &
!shi3;
-- Node name is 'ge13' = ':2'
-- Equation name is 'ge13', type is output
ge13 = DFFE( _EQ006 $ _LC004, GLOBAL( clk1), VCC, VCC, VCC);
_EQ006 = ge0~105 & _LC004 & !_LC006 & _LC007;
-- Node name is ':33' = 'shi0'
-- Equation name is 'shi0', location is LC027, type is buried.
shi0 = TFFE( _EQ007, GLOBAL( clk1), VCC, VCC, VCC);
_EQ007 = ge0~105 & _LC004 & !_LC006 & _LC007;
-- Node name is ':32' = 'shi1~109'
-- Equation name is 'shi1~109', location is LC028, type is buried.
shi1~109 = TFFE( _EQ008, GLOBAL( clk1), VCC, VCC, VCC);
_EQ008 = ge0~105 & !_LC004 & _LC006 & !_LC007 & !shi0 & shi1~109 & !shi2 &
!shi3
# ge0~105 & _LC004 & !_LC006 & _LC007 & shi0;
-- Node name is ':31' = 'shi2'
-- Equation name is 'shi2', location is LC029, type is buried.
shi2 = TFFE( _EQ009, GLOBAL( clk1), VCC, VCC, VCC);
_EQ009 = ge0~105 & _LC004 & !_LC006 & _LC007 & shi0 & shi1~109;
-- Node name is ':30' = 'shi3'
-- Equation name is 'shi3', location is LC030, type is buried.
shi3 = TFFE( _EQ010, GLOBAL( clk1), VCC, VCC, VCC);
_EQ010 = ge0~105 & _LC004 & !_LC006 & _LC007 & shi0 & shi1~109 & shi2;
-- Node name is 'shi10' = ':16'
-- Equation name is 'shi10', type is output
shi10 = TFFE( _EQ011, GLOBAL( clk1), VCC, VCC, VCC);
_EQ011 = ge0~105 & !_LC004 & _LC006 & !_LC007 & !shi0 & shi1~109 & !shi2 &
!shi3 & shi10
# ge0~105 & _LC004 & !_LC006 & _LC007 & shi0 & shi10
# ge0~105 & _LC004 & !_LC006 & _LC007 & !shi0 & !shi10;
-- Node name is 'shi11' = ':14'
-- Equation name is 'shi11', type is output
shi11 = TFFE( _EQ012, GLOBAL( clk1), VCC, VCC, VCC);
_EQ012 = ge0~105 & !_LC004 & _LC006 & !_LC007 & !shi0 & shi1~109 & !shi2 &
!shi3 & shi11
# ge0~105 & _LC004 & !_LC006 & _LC007 & _LC026 & !shi11
# ge0~105 & _LC004 & !_LC006 & _LC007 & !_LC026 & shi11;
-- Node name is 'shi12' = ':12'
-- Equation name is 'shi12', type is output
shi12 = TFFE( _EQ013, GLOBAL( clk1), VCC, VCC, VCC);
_EQ013 = ge0~105 & !_LC004 & _LC006 & !_LC007 & !shi0 & shi1~109 & !shi2 &
!shi3 & shi12
# ge0~105 & _LC004 & !_LC006 & _LC007 & _LC021 & !shi12
# ge0~105 & _LC004 & !_LC006 & _LC007 & !_LC021 & shi12;
-- Node name is 'shi13' = ':10'
-- Equation name is 'shi13', type is output
shi13 = TFFE( _EQ014, GLOBAL( clk1), VCC, VCC, VCC);
_EQ014 = ge0~105 & !_LC004 & _LC006 & !_LC007 & !shi0 & shi1~109 & !shi2 &
!shi3 & shi13
# ge0~105 & _LC004 & !_LC006 & _LC007 & _LC025 & !shi13
# ge0~105 & _LC004 & !_LC006 & _LC007 & !_LC025 & shi13;
-- Node name is '|LPM_ADD_SUB:62|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC007', type is buried
_LC007 = LCELL( ge1~105 $ ge0~105);
-- Node name is '|LPM_ADD_SUB:62|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC006', type is buried
_LC006 = LCELL( ge2~105 $ _EQ015);
_EQ015 = ge0~105 & ge1~105;
-- Node name is '|LPM_ADD_SUB:62|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC004', type is buried
_LC004 = LCELL( ge3~105 $ _EQ016);
_EQ016 = ge0~105 & ge1~105 & ge2~105;
-- Node name is '|LPM_ADD_SUB:91|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC026', type is buried
_LC026 = LCELL( shi1~109 $ shi0);
-- Node name is '|LPM_ADD_SUB:91|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC021', type is buried
_LC021 = LCELL( shi2 $ _EQ017);
_EQ017 = shi0 & shi1~109;
-- Node name is '|LPM_ADD_SUB:91|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried
_LC025 = LCELL( shi3 $ _EQ018);
_EQ018 = shi0 & shi1~109 & shi2;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\shuzizhong05\jishu2.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 6,503K
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