📄 jishu2.rpt
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Project Information e:\shuzizhong05\jishu2.rpt
MAX+plus II Compiler Report File
Version 9.23 3/19/99
Compiled: 11/26/2006 11:45:06
Copyright (C) 1988-1999 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
JISHU2
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
jishu2 EPM7032LC44-6 1 8 0 22 0 68 %
User Pins: 1 8 0
Project Information e:\shuzizhong05\jishu2.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk1' chosen for auto global Clock
Project Information e:\shuzizhong05\jishu2.rpt
** FILE HIERARCHY **
|lpm_add_sub:62|
|lpm_add_sub:62|addcore:adder|
|lpm_add_sub:62|addcore:adder|addcore:adder0|
|lpm_add_sub:62|altshift:result_ext_latency_ffs|
|lpm_add_sub:62|altshift:carry_ext_latency_ffs|
|lpm_add_sub:62|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:91|
|lpm_add_sub:91|addcore:adder|
|lpm_add_sub:91|addcore:adder|addcore:adder0|
|lpm_add_sub:91|altshift:result_ext_latency_ffs|
|lpm_add_sub:91|altshift:carry_ext_latency_ffs|
|lpm_add_sub:91|altshift:oflow_ext_latency_ffs|
Device-Specific Information: e:\shuzizhong05\jishu2.rpt
jishu2
***** Logic for device 'jishu2' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
R R
E E
S S
E E s s
R R g c h h
V V e V G G G l G i i
E E 1 C N N N k N 1 1
D D 0 C D D D 1 D 3 2
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
RESERVED | 7 39 | shi11
RESERVED | 8 38 | shi10
RESERVED | 9 37 | RESERVED
GND | 10 36 | ge13
RESERVED | 11 35 | VCC
RESERVED | 12 EPM7032LC44-6 34 | ge12
RESERVED | 13 33 | ge11
RESERVED | 14 32 | RESERVED
VCC | 15 31 | RESERVED
RESERVED | 16 30 | GND
RESERVED | 17 29 | RESERVED
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V R R R R R
E E E E N C E E E E E
S S S S D C S S S S S
E E E E E E E E E
R R R R R R R R R
V V V V V V V V V
E E E E E E E E E
D D D D D D D D D
N.C. = No Connect, This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\shuzizhong05\jishu2.rpt
jishu2
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 6/16( 37%) 1/16( 6%) 0/16( 0%) 5/36( 13%)
B: LC17 - LC32 16/16(100%) 7/16( 43%) 0/16( 0%) 15/36( 41%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 8/32 ( 25%)
Total logic cells used: 22/32 ( 68%)
Total shareable expanders used: 0/32 ( 0%)
Total Turbo logic cells used: 22/32 ( 68%)
Total shareable expanders not available (n/a): 0/32 ( 0%)
Average fan-in: 6.13
Total fan-in: 135
Total input pins required: 1
Total output pins required: 8
Total bidirectional pins required: 0
Total logic cells required: 22
Total flipflops required: 16
Total product terms required: 43
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information: e:\shuzizhong05\jishu2.rpt
jishu2
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
43 - - INPUT G 0 0 0 0 0 0 0 clk1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\shuzizhong05\jishu2.rpt
jishu2
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
4 1 A FF + t 0 0 0 0 1 0 0 ge10
33 24 B FF + t 0 0 0 0 4 0 0 ge11
34 23 B FF + t 0 0 0 0 8 0 0 ge12
36 22 B FF + t 0 0 0 0 4 0 0 ge13
38 20 B FF + t 0 0 0 0 9 1 0 shi10
39 19 B FF + t 0 0 0 0 10 1 0 shi11
40 18 B FF + t 0 0 0 0 10 1 0 shi12
41 17 B FF + t 0 0 0 0 10 1 0 shi13
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\shuzizhong05\jishu2.rpt
jishu2
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(11) 7 A SOFT t 0 0 0 0 2 7 6 |LPM_ADD_SUB:62|addcore:adder|addcore:adder0|result_node1
(9) 6 A SOFT t 0 0 0 0 3 7 6 |LPM_ADD_SUB:62|addcore:adder|addcore:adder0|result_node2
(7) 4 A SOFT t 0 0 0 0 4 7 7 |LPM_ADD_SUB:62|addcore:adder|addcore:adder0|result_node3
(31) 26 B SOFT t 0 0 0 0 2 1 0 |LPM_ADD_SUB:91|addcore:adder|addcore:adder0|result_node1
(37) 21 B SOFT t 0 0 0 0 3 1 0 |LPM_ADD_SUB:91|addcore:adder|addcore:adder0|result_node2
(32) 25 B SOFT t 0 0 0 0 4 1 0 |LPM_ADD_SUB:91|addcore:adder|addcore:adder0|result_node3
(12) 8 A DFFE + t 0 0 0 0 4 0 1 ge3~105 (:26)
(24) 32 B DFFE + t 0 0 0 0 8 0 3 ge2~105 (:27)
(25) 31 B DFFE + t 0 0 0 0 4 0 4 ge1~105 (:28)
(8) 5 A TFFE + t 0 0 0 0 0 8 10 ge0~105 (:29)
(26) 30 B TFFE + t 0 0 0 0 7 5 3 shi3 (:30)
(27) 29 B TFFE + t 0 0 0 0 6 5 5 shi2 (:31)
(28) 28 B TFFE + t 0 0 0 0 8 5 7 shi1~109 (:32)
(29) 27 B TFFE + t 0 0 0 0 4 5 7 shi0 (:33)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\shuzizhong05\jishu2.rpt
jishu2
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----------- LC1 ge10
| +--------- LC7 |LPM_ADD_SUB:62|addcore:adder|addcore:adder0|result_node1
| | +------- LC6 |LPM_ADD_SUB:62|addcore:adder|addcore:adder0|result_node2
| | | +----- LC4 |LPM_ADD_SUB:62|addcore:adder|addcore:adder0|result_node3
| | | | +--- LC8 ge3~105
| | | | | +- LC5 ge0~105
| | | | | |
| | | | | | Other LABs fed by signals
| | | | | | that feed LAB 'A'
LC | | | | | | | A B | Logic cells that feed LAB 'A':
LC4 -> - - - - * - | * * | <-- |LPM_ADD_SUB:62|addcore:adder|addcore:adder0|result_node3
LC8 -> - - - * - - | * - | <-- ge3~105
LC5 -> * * * * * * | * * | <-- ge0~105
Pin
43 -> - - - - - - | - - | <-- clk1
LC32 -> - - * * * - | * - | <-- ge2~105
LC31 -> - * * * * - | * - | <-- ge1~105
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\shuzizhong05\jishu2.rpt
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