xianshi.vhd

MAX+plus II 9.23 Baseline

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity xianshi is
port(four_in: in std_logic_vector(3 downto 0);
         a,b,c,d,e,f,g: out std_logic);
end xianshi;

architecture zong of xianshi is
signal seven_out: std_logic_vector(6 downto 0);
begin
  process(four_in)
  begin
    case four_in is
      when"0000"=>seven_out<="1111110";
      when"0001"=>seven_out<="0110000";
      when"0010"=>seven_out<="1101101";
      when"0011"=>seven_out<="1111001";
      when"0100"=>seven_out<="0110011";
      when"0101"=>seven_out<="1011011";
      when"0110"=>seven_out<="1011111";
      when"0111"=>seven_out<="1110000";
      when"1000"=>seven_out<="1111111";
      when"1001"=>seven_out<="1111011";
      when others=>seven_out<="0000000";
    end case;
  end process;
  a<=seven_out(6);
  b<=seven_out(5);
  c<=seven_out(4);
  d<=seven_out(3);
  e<=seven_out(2);
  f<=seven_out(1);
  g<=seven_out(0);
end zong;