can_top.syr

很好的几个FPGA工程设计实例，Verilog编写

Optimizing unit <can_fifo> ...

Optimizing unit <can_registers> ...

Optimizing unit <can_bsp> ...
Loading device for application Xst from file '2s300e.nph' in environment C:/Program Files/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Register i_can_bsp_node_bus_off_q equivalent to i_can_registers_node_bus_off_q has been removed
Found area constraint ratio of 100 (+ 5) on block can_top, actual ratio is 30.
FlipFlop i_can_btl_sampled_bit has been replicated 1 time(s)
FlipFlop addr_latched_0 has been replicated 2 time(s)
FlipFlop addr_latched_2 has been replicated 4 time(s)
FlipFlop addr_latched_4 has been replicated 4 time(s)
FlipFlop addr_latched_1 has been replicated 3 time(s)
FlipFlop addr_latched_3 has been replicated 2 time(s)
FlipFlop addr_latched_0 has been replicated 1 time(s)
FlipFlop i_can_registers_MODE_REG0_data_out_0 has been replicated 1 time(s)
FlipFlop i_can_bsp_tx_pointer_21 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : can_top.ngr
Top Level Output File Name         : can_top
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 18

Macro Statistics :
# Registers                        : 243
#      1-bit register              : 184
#      15-bit register             : 1
#      2-bit register              : 1
#      3-bit register              : 14
#      4-bit register              : 3
#      6-bit register              : 1
#      7-bit register              : 1
#      8-bit register              : 36
#      9-bit register              : 2
# Counters                         : 10
#      4-bit up counter            : 2
#      5-bit up counter            : 1
#      6-bit up counter            : 5
#      8-bit up counter            : 1
#      9-bit up counter            : 1
# Multiplexers                     : 27
#      1-bit 16-to-1 multiplexer   : 1
#      1-bit 19-to-1 multiplexer   : 2
#      1-bit 39-to-1 multiplexer   : 1
#      1-bit 64-to-1 multiplexer   : 2
#      2-to-1 multiplexer          : 20
#      8-bit 8-to-1 multiplexer    : 1
# Tristates                        : 2
#      1-bit tristate buffer       : 1
#      8-bit tristate buffer       : 1
# Adders/Subtractors               : 21
#      10-bit subtractor           : 1
#      4-bit adder                 : 3
#      4-bit adder carry out       : 1
#      4-bit subtractor            : 2
#      6-bit adder                 : 4
#      6-bit adder carry out       : 1
#      6-bit subtractor            : 2
#      7-bit addsub                : 1
#      7-bit subtractor            : 1
#      9-bit addsub                : 1
#      9-bit subtractor            : 4
# Comparators                      : 47
#      10-bit comparator less      : 1
#      11-bit comparator equal     : 1
#      15-bit comparator not equal : 1
#      3-bit comparator equal      : 1
#      3-bit comparator less       : 7
#      4-bit comparator equal      : 1
#      4-bit comparator less       : 4
#      6-bit comparator equal      : 1
#      6-bit comparator greater    : 2
#      6-bit comparator less       : 2
#      8-bit comparator equal      : 2
#      8-bit comparator greatequal : 2
#      8-bit comparator greater    : 1
#      8-bit comparator less       : 1
#      8-bit comparator lessequal  : 2
#      8-bit comparator not equal  : 2
#      9-bit comparator equal      : 2
#      9-bit comparator greatequal : 8
#      9-bit comparator greater    : 3
#      9-bit comparator less       : 2
#      9-bit comparator lessequal  : 1

Cell Usage :
# BELS                             : 2125
#      BUF                         : 3
#      GND                         : 1
#      LUT1                        : 98
#      LUT2                        : 194
#      LUT2_D                      : 4
#      LUT2_L                      : 14
#      LUT3                        : 460
#      LUT3_D                      : 16
#      LUT3_L                      : 22
#      LUT4                        : 629
#      LUT4_D                      : 20
#      LUT4_L                      : 100
#      MUXCY                       : 248
#      MUXF5                       : 100
#      MUXF6                       : 39
#      VCC                         : 1
#      XORCY                       : 176
# FlipFlops/Latches                : 646
#      FD                          : 9
#      FDC                         : 9
#      FDCE                        : 240
#      FDCE_1                      : 24
#      FDCPE                       : 61
#      FDE                         : 271
#      FDPE                        : 17
#      FDRE                        : 15
# RAMS                             : 3
#      RAMB4_S1_S1                 : 1
#      RAMB4_S4_S4                 : 1
#      RAMB4_S8_S8                 : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 17
#      IBUF                        : 6
#      IOBUF                       : 8
#      OBUF                        : 2
#      OBUFT                       : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s300epq208-6 

 Number of Slices:                     864  out of   3072    28%  
 Number of Slice Flip Flops:           646  out of   6144    10%  
 Number of 4 input LUTs:              1557  out of   6144    25%  
 Number of bonded IOBs:                 17  out of    146    11%  
 Number of BRAMs:                        3  out of      8    37%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_i                              | BUFGP                  | 649   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 29.552ns (Maximum Frequency: 33.839MHz)
   Minimum input arrival time before clock: 20.316ns
   Maximum output required time after clock: 10.090ns
   Maximum combinational path delay: 13.541ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk_i'
Delay:               14.776ns (Levels of Logic = 5)
  Source:            addr_latched_2 (FF)
  Destination:       i_can_registers_data_out_7 (FF)
  Source Clock:      clk_i falling
  Destination Clock: clk_i rising

  Data Path: addr_latched_2 to i_can_registers_data_out_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE_1:C->Q          19   0.992   2.950  addr_latched_2 (addr_latched_2)
     LUT3_D:I2->O         11   0.468   2.350  i_can_registers_Ker316641 (i_can_registers_N31666)
     LUT3_D:I2->O         12   0.468   2.450  i_can_registers__n00621 (i_can_registers__n0062)
     LUT4:I3->O            1   0.468   0.920  i_can_registers_Ker3144451 (CHOICE1929)
     LUT4:I2->O            8   0.468   2.050  i_can_registers_Ker31444103 (i_can_registers_N31446)
     LUT4_L:I3->LO         1   0.468   0.000  i_can_registers_data_out_tmp<5>242 (i_can_registers_data_out_tmp<5>)
     FDCE:D                    0.724          i_can_registers_data_out_5
    ----------------------------------------
    Total                     14.776ns (4.056ns logic, 10.720ns route)
                                       (27.4% logic, 72.6% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk_i'
Offset:              20.316ns (Levels of Logic = 10)
  Source:            rx_i (PAD)
  Destination:       i_can_bsp_tx_err_cnt_6 (FF)
  Destination Clock: clk_i rising

  Data Path: rx_i to i_can_bsp_tx_err_cnt_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             3   0.797   1.320  rx_i_IBUF (rx_i_IBUF)
     LUT4_D:I0->O          6   0.468   1.850  i_can_btl_Ker287381 (i_can_btl_N28740)
     LUT4_D:I2->O          6   0.468   1.850  i_can_btl_Ker287481 (i_can_btl_N28750)
     LUT4_D:I3->LO         1   0.468   0.100  i_can_btl_go_sync1 (N55900)
     LUT4:I3->O           11   0.468   2.350  i_can_bsp_error_frame_ended1 (i_can_bsp_error_frame_ended)
     LUT4:I1->O           13   0.468   2.550  i_can_bsp_go_rx_inter (i_can_bsp_go_rx_inter)
     LUT4_D:I0->LO         2   0.468   0.100  i_can_bsp_tx_successful (N56036)
     LUT4:I1->O           10   0.468   2.250  i_can_bsp__n047524 (i_can_bsp__n0475)
     LUT4_L:I3->LO         1   0.468   0.100  i_can_bsp__n068567 (CHOICE1846)
     LUT2:I1->O            9   0.468   2.150  i_can_bsp__n068579 (i_can_bsp__n0685)
     FDCE:CE                   0.687          i_can_bsp_tx_err_cnt_0
    ----------------------------------------
    Total                     20.316ns (5.696ns logic, 14.620ns route)
                                       (28.0% logic, 72.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk_i'
Offset:              10.090ns (Levels of Logic = 3)
  Source:            i_can_registers_CLOCK_DIVIDER_REG_LOW_data_out_1 (FF)
  Destination:       clkout_o (PAD)
  Source Clock:      clk_i rising

  Data Path: i_can_registers_CLOCK_DIVIDER_REG_LOW_data_out_1 to clkout_o
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              5   0.992   1.720  i_can_registers_CLOCK_DIVIDER_REG_LOW_data_out_1 (i_can_registers_CLOCK_DIVIDER_REG_LOW_data_out_1)
     LUT4:I1->O            1   0.468   0.920  i_can_registers_clkout_SW0 (N39408)
     LUT4:I2->O            1   0.468   0.920  i_can_registers_clkout (clkout_o_OBUF)
     OBUF:I->O                 4.602          clkout_o_OBUF (clkout_o)
    ----------------------------------------
    Total                     10.090ns (6.530ns logic, 3.560ns route)
                                       (64.7% logic, 35.3% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               13.541ns (Levels of Logic = 4)
  Source:            clk_i (PAD)
  Destination:       clkout_o (PAD)

  Data Path: clk_i to clkout_o
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     BUFGP:I->O          653   0.663   5.500  clk_i_BUFGP (clk_i_BUFGP)
     LUT4:I2->O            1   0.468   0.920  i_can_registers_clkout_SW0 (N39408)
     LUT4:I2->O            1   0.468   0.920  i_can_registers_clkout (clkout_o_OBUF)
     OBUF:I->O                 4.602          clkout_o_OBUF (clkout_o)
    ----------------------------------------
    Total                     13.541ns (6.201ns logic, 7.340ns route)
                                       (45.8% logic, 54.2% route)

=========================================================================
CPU : 31.15 / 31.53 s | Elapsed : 31.00 / 31.00 s
 
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Total memory usage is 91176 kilobytes