can_top.syr

很好的几个FPGA工程设计实例，Verilog编写

    Found 6-bit up counter for signal <bit_cnt>.
    Found 1-bit register for signal <bit_err_latched>.
    Found 3-bit register for signal <bit_stuff_cnt>.
    Found 1-bit register for signal <bit_stuff_cnt_en>.
    Found 3-bit register for signal <bit_stuff_cnt_tx>.
    Found 1-bit register for signal <bus_free>.
    Found 4-bit register for signal <bus_free_cnt>.
    Found 1-bit register for signal <bus_free_cnt_en>.
    Found 3-bit up counter for signal <byte_cnt>.
    Found 1-bit register for signal <crc_enable>.
    Found 1-bit register for signal <crc_err>.
    Found 15-bit register for signal <crc_in>.
    Found 4-bit up counter for signal <data_cnt>.
    Found 4-bit register for signal <data_len>.
    Found 3-bit up counter for signal <delayed_dominant_cnt>.
    Found 1-bit register for signal <enable_error_cnt2>.
    Found 1-bit register for signal <enable_overload_cnt2>.
    Found 3-bit up counter for signal <eof_cnt>.
    Found 1-bit register for signal <error_capture_code_blocked>.
    Found 3-bit up counter for signal <error_cnt1>.
    Found 3-bit up counter for signal <error_cnt2>.
    Found 1-bit register for signal <error_flag_over_blocked>.
    Found 1-bit register for signal <error_frame>.
    Found 1-bit register for signal <error_frame_q>.
    Found 1-bit register for signal <finish_msg>.
    Found 1-bit register for signal <form_err_latched>.
    Found 1-bit register for signal <go_early_tx_latched>.
    Found 3-bit up counter for signal <header_cnt>.
    Found 29-bit register for signal <id>.
    Found 1-bit register for signal <ide>.
    Found 1-bit register for signal <node_bus_off_q>.
    Found 3-bit up counter for signal <overload_cnt1>.
    Found 3-bit up counter for signal <overload_cnt2>.
    Found 1-bit register for signal <overload_frame>.
    Found 1-bit register for signal <overload_frame_blocked>.
    Found 3-bit register for signal <passive_cnt>.
    Found 1-bit register for signal <reset_mode_q>.
    Found 1-bit register for signal <rtr1>.
    Found 1-bit register for signal <rtr2>.
    Found 1-bit register for signal <rule3_exc1_1>.
    Found 1-bit register for signal <rule3_exc1_2>.
    Found 1-bit register for signal <rule3_exc2>.
    Found 1-bit register for signal <rx_ack>.
    Found 1-bit register for signal <rx_ack_lim>.
    Found 1-bit register for signal <rx_crc>.
    Found 1-bit register for signal <rx_crc_lim>.
    Found 1-bit register for signal <rx_data>.
    Found 1-bit register for signal <rx_dlc>.
    Found 1-bit register for signal <rx_eof>.
    Found 1-bit register for signal <rx_err_cnt_blocked>.
    Found 1-bit register for signal <rx_id1>.
    Found 1-bit register for signal <rx_id2>.
    Found 1-bit register for signal <rx_ide>.
    Found 1-bit register for signal <rx_inter>.
    Found 1-bit register for signal <rx_r0>.
    Found 1-bit register for signal <rx_r1>.
    Found 1-bit register for signal <rx_rtr1>.
    Found 1-bit register for signal <rx_rtr2>.
    Found 3-bit comparator less for signal <storing_header>.
    Found 1-bit register for signal <stuff_err_latched>.
    Found 3-bit up counter for signal <susp_cnt>.
    Found 1-bit register for signal <susp_cnt_en>.
    Found 1-bit register for signal <suspend>.
    Found 8-bit register for signal <tmp_data>.
    Found 64-bit register for signal <tmp_fifo>.
    Found 1-bit register for signal <transmitter>.
    Found 1-bit register for signal <tx_point_q>.
    Found 6-bit up counter for signal <tx_pointer>.
    Found 1-bit register for signal <tx_q>.
    Found 1-bit register for signal <tx_state>.
    Found 1-bit register for signal <waiting_for_bus_free>.
    Found 1-bit register for signal <wr_fifo>.
    Found 1-bit register for signal <write_data_to_tmp_fifo>.
    Found 1 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  13 Counter(s).
	inferred 215 D-type flip-flop(s).
	inferred  14 Adder/Subtracter(s).
	inferred  35 Comparator(s).
	inferred  15 Multiplexer(s).
Unit <can_bsp> synthesized.


Synthesizing Unit <can_btl>.
    Related source file is can_btl.v.
    Found 1-bit register for signal <clk_en>.
    Found 1-bit register for signal <sample_point>.
    Found 1-bit register for signal <sampled_bit>.
    Found 1-bit register for signal <sampled_bit_q>.
    Found 10-bit subtractor for signal <$n0000> created at line 204.
    Found 9-bit subtractor for signal <$n0003> created at line 307.
    Found 11-bit comparator equal for signal <$n0007> created at line 204.
    Found 8-bit comparator greater for signal <$n0030> created at line 300.
    Found 8-bit comparator equal for signal <$n0034> created at line 226.
    Found 8-bit comparator equal for signal <$n0035> created at line 224.
    Found 4-bit adder for signal <$n0038> created at line 300.
    Found 8-bit comparator not equal for signal <$n0041> created at line 331.
    Found 8-bit comparator not equal for signal <$n0042> created at line 357.
    Found 2-bit adder carry out for signal <$n0043> created at line 300.
    Found 4-bit adder carry out for signal <$n0044> created at line 331.
    Found 6-bit adder carry out for signal <$n0045> created at line 194.
    Found 9-bit up counter for signal <clk_cnt>.
    Found 4-bit register for signal <delay>.
    Found 8-bit up counter for signal <quant_cnt>.
    Found 1-bit register for signal <resync_blocked>.
    Found 1-bit register for signal <resync_latched>.
    Found 2-bit register for signal <sample>.
    Found 1-bit register for signal <seg1>.
    Found 1-bit register for signal <seg2>.
    Found 1-bit register for signal <sync>.
    Found 1-bit register for signal <sync_blocked>.
    Found 10-bit comparator less for signal <sync_window>.
    Found 1 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   2 Counter(s).
	inferred  16 D-type flip-flop(s).
	inferred   6 Adder/Subtracter(s).
	inferred   7 Comparator(s).
	inferred   1 Multiplexer(s).
Unit <can_btl> synthesized.


Synthesizing Unit <can_registers>.
    Related source file is can_registers.v.
WARNING:Xst:646 - Signal <info_empty_q> is assigned but never used.
    Found 8-bit register for signal <data_out>.
    Found 1-bit register for signal <single_shot_transmission>.
    Found 3-bit comparator equal for signal <$n0015> created at line 748.
    Found 1-bit xor2 for signal <$n0178> created at line 1143.
    Found 1-bit xor2 for signal <$n0179> created at line 1143.
    Found 1-bit register for signal <arbitration_lost_irq>.
    Found 1-bit register for signal <bus_error_irq>.
    Found 3-bit up counter for signal <clkout_cnt>.
    Found 1-bit register for signal <clkout_tmp>.
    Found 1-bit register for signal <data_overrun_irq>.
    Found 1-bit register for signal <error_irq>.
    Found 1-bit register for signal <error_passive_irq>.
    Found 1-bit register for signal <error_status_q>.
    Found 1-bit register for signal <node_bus_off_q>.
    Found 1-bit register for signal <node_error_passive_q>.
    Found 1-bit register for signal <overrun_q>.
    Found 1-bit register for signal <overrun_status>.
    Found 1-bit register for signal <receive_buffer_status>.
    Found 1-bit register for signal <receive_irq>.
    Found 1-bit register for signal <transmission_complete>.
    Found 1-bit register for signal <transmit_buffer_status>.
    Found 1-bit register for signal <transmit_buffer_status_q>.
    Found 1-bit register for signal <transmit_irq>.
    Found 1-bit register for signal <tx_successful_q>.
    Found 4 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Counter(s).
	inferred  27 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   4 Multiplexer(s).
Unit <can_registers> synthesized.


Synthesizing Unit <can_top>.
    Related source file is can_top.v.
WARNING:Xst:646 - Signal <clk_en> is assigned but never used.
WARNING:Xst:646 - Signal <tx_err_cnt_dummy> is assigned but never used.
WARNING:Xst:646 - Signal <resync> is assigned but never used.
WARNING:Xst:646 - Signal <rx_err_cnt_dummy> is assigned but never used.
    Found 1-bit tristate buffer for signal <tx_o>.
    Found 8-bit tristate buffer for signal <port_0_io>.
    Found 8-bit comparator greatequal for signal <$n0005> created at line 636.
    Found 8-bit comparator lessequal for signal <$n0006> created at line 636.
    Found 8-bit comparator greatequal for signal <$n0007> created at line 636.
    Found 8-bit comparator lessequal for signal <$n0008> created at line 636.
    Found 8-bit register for signal <addr_latched>.
    Found 8-bit register for signal <data_out>.
    Found 1-bit register for signal <rd_i_q>.
    Found 1-bit register for signal <wr_i_q>.
    Found 8 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  18 D-type flip-flop(s).
	inferred   4 Comparator(s).
	inferred   8 Multiplexer(s).
	inferred   9 Tristate(s).
Unit <can_top> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 211
  1-bit register                   : 160
  8-bit register                   : 37
  2-bit register                   : 1
  3-bit register                   : 5
  4-bit register                   : 3
  9-bit register                   : 2
  6-bit register                   : 1
  7-bit register                   : 1
  15-bit register                  : 1
# Counters                         : 21
  4-bit up counter                 : 2
  6-bit up counter                 : 5
  7-bit updown counter             : 1
  3-bit up counter                 : 10
  5-bit up counter                 : 1
  9-bit up counter                 : 1
  8-bit up counter                 : 1
# Multiplexers                     : 16
  1-bit 16-to-1 multiplexer        : 1
  1-bit 19-to-1 multiplexer        : 2
  2-to-1 multiplexer               : 9
  1-bit 39-to-1 multiplexer        : 1
  1-bit 64-to-1 multiplexer        : 2
  8-bit 8-to-1 multiplexer         : 1
# Tristates                        : 2
  1-bit tristate buffer            : 1
  8-bit tristate buffer            : 1
# Adders/Subtractors               : 25
  6-bit adder                      : 4
  4-bit adder                      : 3
  4-bit subtractor                 : 2
  6-bit subtractor                 : 2
  3-bit adder                      : 3
  9-bit subtractor                 : 4
  10-bit subtractor                : 1
  2-bit adder carry out            : 1
  4-bit adder carry out            : 1
  6-bit adder carry out            : 1
  7-bit addsub                     : 1
  7-bit subtractor                 : 1
  9-bit addsub                     : 1
# Comparators                      : 47
  3-bit comparator less            : 7
  4-bit comparator less            : 4
  6-bit comparator less            : 2
  6-bit comparator equal           : 1
  15-bit comparator not equal      : 1
  9-bit comparator greatequal      : 8
  9-bit comparator lessequal       : 1
  9-bit comparator greater         : 3
  9-bit comparator less            : 2
  8-bit comparator less            : 1
  10-bit comparator less           : 1
  11-bit comparator equal          : 1
  8-bit comparator greater         : 1
  8-bit comparator equal           : 2
  8-bit comparator not equal       : 2
  3-bit comparator equal           : 1
  8-bit comparator greatequal      : 2
  8-bit comparator lessequal       : 2
  6-bit comparator greater         : 2
  9-bit comparator equal           : 2
  4-bit comparator equal           : 1
# Xors                             : 101
  1-bit xor2                       : 101

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <can_top> ...

Optimizing unit <can_crc> ...

Optimizing unit <can_acf> ...

Optimizing unit <can_btl> ...