can_fifo.syr

很好的几个FPGA工程设计实例，Verilog编写

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : can_fifo.ngr
Top Level Output File Name         : can_fifo
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 40

Macro Statistics :
# Registers                        : 5
#      1-bit register              : 2
#      6-bit register              : 1
#      7-bit register              : 2
# Counters                         : 4
#      4-bit up counter            : 1
#      6-bit up counter            : 3
# Multiplexers                     : 1
#      2-to-1 multiplexer          : 1
# Adders/Subtractors               : 6
#      6-bit adder                 : 2
#      6-bit subtractor            : 1
#      7-bit addsub                : 2
#      7-bit subtractor            : 1

Cell Usage :
# BELS                             : 228
#      GND                         : 1
#      LUT1                        : 13
#      LUT2                        : 31
#      LUT2_L                      : 15
#      LUT3                        : 13
#      LUT3_D                      : 1
#      LUT3_L                      : 8
#      LUT4                        : 26
#      LUT4_D                      : 3
#      LUT4_L                      : 1
#      MUXCY                       : 55
#      MUXF5                       : 2
#      VCC                         : 1
#      XORCY                       : 58
# FlipFlops/Latches                : 44
#      FDC                         : 1
#      FDCE                        : 21
#      FDCPE                       : 22
# RAMS                             : 3
#      RAMB4_S1_S1                 : 1
#      RAMB4_S4_S4                 : 1
#      RAMB4_S8_S8                 : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 36
#      IBUF                        : 19
#      OBUF                        : 17
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s300epq208-6 

 Number of Slices:                      64  out of   3072     2%  
 Number of Slice Flip Flops:            44  out of   6144     0%  
 Number of 4 input LUTs:               111  out of   6144     1%  
 Number of bonded IOBs:                 36  out of    146    24%  
 Number of BRAMs:                        3  out of      8    37%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 47    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 13.017ns (Maximum Frequency: 76.823MHz)
   Minimum input arrival time before clock: 10.841ns
   Maximum output required time after clock: 11.718ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               13.017ns (Levels of Logic = 13)
  Source:            fifo_cnt_0 (FF)
  Destination:       fifo_cnt_6 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: fifo_cnt_0 to fifo_cnt_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             4   0.992   1.520  fifo_cnt_0 (fifo_cnt_0)
     LUT3_L:I0->LO         1   0.468   0.100  Ker3541_SW0 (N3938)
     LUT4:I3->O           12   0.468   2.450  Ker3541 (N3543)
     LUT4_D:I1->O          7   0.468   1.950  _n00341 (_n0034)
     LUT2_L:I1->LO         1   0.468   0.100  Maddsub__n0020_inst_lut3_01_SW0 (N4171)
     LUT4:I3->O            1   0.468   0.000  Maddsub__n0020_inst_lut3_01 (Maddsub__n0020_inst_lut3_0)
     MUXCY:S->O            1   0.515   0.000  Maddsub__n0020_inst_cy_12 (Maddsub__n0020_inst_cy_12)
     MUXCY:CI->O           1   0.058   0.000  Maddsub__n0020_inst_cy_13 (Maddsub__n0020_inst_cy_13)
     MUXCY:CI->O           1   0.058   0.000  Maddsub__n0020_inst_cy_14 (Maddsub__n0020_inst_cy_14)
     MUXCY:CI->O           1   0.058   0.000  Maddsub__n0020_inst_cy_15 (Maddsub__n0020_inst_cy_15)
     MUXCY:CI->O           1   0.058   0.000  Maddsub__n0020_inst_cy_16 (Maddsub__n0020_inst_cy_16)
     MUXCY:CI->O           0   0.058   0.000  Maddsub__n0020_inst_cy_17 (Maddsub__n0020_inst_cy_17)
     XORCY:CI->O           1   0.648   0.920  Maddsub__n0020_inst_sum_19 (_n0020<6>)
     LUT2_L:I0->LO         1   0.468   0.000  _n0015<6>1 (_n0015<6>)
     FDCE:D                    0.724          fifo_cnt_6
    ----------------------------------------
    Total                     13.017ns (5.977ns logic, 7.040ns route)
                                       (45.9% logic, 54.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset:              10.841ns (Levels of Logic = 12)
  Source:            wr (PAD)
  Destination:       fifo_cnt_6 (FF)
  Destination Clock: clk rising

  Data Path: wr to fifo_cnt_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            21   0.797   3.025  wr_IBUF (wr_IBUF)
     LUT4_D:I2->O          7   0.468   1.950  _n00341 (_n0034)
     LUT2_L:I1->LO         1   0.468   0.100  Maddsub__n0020_inst_lut3_01_SW0 (N4171)
     LUT4:I3->O            1   0.468   0.000  Maddsub__n0020_inst_lut3_01 (Maddsub__n0020_inst_lut3_0)
     MUXCY:S->O            1   0.515   0.000  Maddsub__n0020_inst_cy_12 (Maddsub__n0020_inst_cy_12)
     MUXCY:CI->O           1   0.058   0.000  Maddsub__n0020_inst_cy_13 (Maddsub__n0020_inst_cy_13)
     MUXCY:CI->O           1   0.058   0.000  Maddsub__n0020_inst_cy_14 (Maddsub__n0020_inst_cy_14)
     MUXCY:CI->O           1   0.058   0.000  Maddsub__n0020_inst_cy_15 (Maddsub__n0020_inst_cy_15)
     MUXCY:CI->O           1   0.058   0.000  Maddsub__n0020_inst_cy_16 (Maddsub__n0020_inst_cy_16)
     MUXCY:CI->O           0   0.058   0.000  Maddsub__n0020_inst_cy_17 (Maddsub__n0020_inst_cy_17)
     XORCY:CI->O           1   0.648   0.920  Maddsub__n0020_inst_sum_19 (_n0020<6>)
     LUT2_L:I0->LO         1   0.468   0.000  _n0015<6>1 (_n0015<6>)
     FDCE:D                    0.724          fifo_cnt_6
    ----------------------------------------
    Total                     10.841ns (4.846ns logic, 5.995ns route)
                                       (44.7% logic, 55.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              11.718ns (Levels of Logic = 4)
  Source:            info_cnt_2 (FF)
  Destination:       info_empty (PAD)
  Source Clock:      clk rising

  Data Path: info_cnt_2 to info_empty
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             3   0.992   1.320  info_cnt_2 (info_cnt_2)
     LUT3_L:I0->LO         1   0.468   0.100  Ker3546_SW0 (N3859)
     LUT4:I3->O            9   0.468   2.150  Ker3546 (N3548)
     LUT2:I1->O            2   0.468   1.150  info_empty1 (info_empty_OBUF)
     OBUF:I->O                 4.602          info_empty_OBUF (info_empty)
    ----------------------------------------
    Total                     11.718ns (6.998ns logic, 4.720ns route)
                                       (59.7% logic, 40.3% route)

=========================================================================
CPU : 3.90 / 4.32 s | Elapsed : 3.00 / 4.00 s
 
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Total memory usage is 63272 kilobytes