firmware.npl

来自「很好的几个FPGA工程设计实例，Verilog编写」· NPL 代码 · 共 33 行

JDF F
// Created by Project Navigator ver 1.0
PROJECT Firmware
DESIGN firmware Normal
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s15
DEVICETIME 0
DEVPKG cs144
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
FLOW XST VHDL
FLOWTIME 0
STIMULUS usbsoftlock_TB.vhd Normal
MODULE IOSwitch.vhd
MODSTYLE ioswitch Normal
MODULE USBSoftLock.vhd
MODSTYLE usbsoftlock Normal
MODULE FrequencyDivider.vhd
MODSTYLE frequencydivider Normal
MODULE RequestHandler.vhd
MODSTYLE requesthandler Normal
MODULE DeviceTranseiver.vhd
MODSTYLE devicetranseiver Normal
MODULE EdgeController.vhd
MODSTYLE edgecontroller Normal
LIBFILE USB_Package.vhd work ***
LIBFILE PDIUSBD12_Package.vhd work ***
DEPASSOC usbsoftlock USBSoftLock_ucf.ucf SYSTEM
[STRATEGY-LIST]
Normal=True