baudrate_generator_tb.vhd

很好的几个FPGA工程设计实例，Verilog编写

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--
-- Title       : Test Bench for baudrate_generator
-- Design      : UART
-- Author      : Xinghua Lou
-- Company     : Tsinghua University
--
---------------------------------------------------------------------------------------------------
--
-- File        : $DSN\src\TestBench\baudrate_generator_TB.vhd
-- Generated   : 4/12/2005, 3:49 PM
-- From        : $DSN\src\baudrate_generator.vhd
-- By          : Active-HDL Built-in Test Bench Generator ver. 1.2s
--
---------------------------------------------------------------------------------------------------
--
-- Description : Automatically generated Test Bench for baudrate_generator_tb
--
---------------------------------------------------------------------------------------------------

library ieee;
use work.uart_package.all;
use ieee.std_logic_1164.all;

	-- Add your library and packages declaration here ...

entity baudrate_generator_tb is
	-- Generic declarations of the tested unit
		generic(
		FULL_PULSE_COUNT : BD_COUNT := 5208;
		RISE_PULSE_COUNT : BD_COUNT := 2604 );
end baudrate_generator_tb;

architecture TB_ARCHITECTURE of baudrate_generator_tb is
	-- Component declaration of the tested unit
	component baudrate_generator
		generic(
		FULL_PULSE_COUNT : BD_COUNT := 5208;
		RISE_PULSE_COUNT : BD_COUNT := 2604 );
	port(
		clk : in std_logic;
		reset_n : in std_logic;
		ce : in std_logic;
		bg_out : out std_logic;
		indicator : out std_logic );
	end component;

	-- Stimulus signals - signals mapped to the input and inout ports of tested entity
	signal clk : std_logic := '0';
	signal reset_n : std_logic;
	signal ce : std_logic;
	-- Observed signals - signals mapped to the output ports of tested entity
	signal bg_out : std_logic;
	signal indicator : std_logic;

	-- Add your code here ...

begin

	-- Unit Under Test port map
	UUT : baudrate_generator
		generic map (
			FULL_PULSE_COUNT => 10,
			RISE_PULSE_COUNT => 5
		)

		port map (
			clk => clk,
			reset_n => reset_n,
			ce => ce,
			bg_out => bg_out,
			indicator => indicator
		);

	-- Add your stimulus here ...
	-- 产生时钟信号
	clk_gen : process
	begin
		clk <= not clk;
		wait for 50 ns;
	end process;

	-- 测试主流程
	main: process
	begin
		reset_n <= '0';	
		ce <= '0';
		wait for 100 ns; 
		reset_n <= '1';	
		wait for 100 ns; 
		ce <= '1';
		wait;
		
	end process;
	
end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_baudrate_generator of baudrate_generator_tb is
	for TB_ARCHITECTURE
		for UUT : baudrate_generator
			use entity work.baudrate_generator(baudrate_generator);
		end for;
	end for;
end TESTBENCH_FOR_baudrate_generator;