uart.npl

很好的几个FPGA工程设计实例，Verilog编写

JDF G
// Converted from an earlier version by Project Navigator version 5
PROJECT UART
DESIGN uart Normal
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s15
DEVICETIME 0
DEVPKG cs144
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
STIMULUS parity_verifier_TB.vhd Normal
STIMULUS counter_TB.vhd Normal
STIMULUS shift_register_TB.vhd Normal
STIMULUS baudrate_generator_TB.vhd Normal
STIMULUS switch_bus_TB.vhd Normal
STIMULUS uart_top_tb.vhd Normal
STIMULUS detector_TB.vhd Normal
MODULE parity_verifier.vhd
MODSTYLE parity_verifier Normal
MODULE counter.vhd
MODSTYLE counter Normal
MODULE uart_core.vhd
MODSTYLE uart_core Normal
MODULE detector.vhd
MODSTYLE detector Normal
MODULE uart_top.vhd
MODSTYLE uart_top Normal
MODULE shift_register.vhd
MODSTYLE shift_register Normal
MODULE switch.vhd
MODSTYLE switch Normal
MODULE baudrate_generator.vhd
MODSTYLE baudrate_generator Normal
MODULE switch_bus.vhd
MODSTYLE switch_bus Normal
LIBFILE UART_PACKAGE.vhd work ***
[STRATEGY-LIST]
Normal=True