fadsu2.v

简单的8位CPU

`resetall
`timescale 1 ns / 1 ps

`celldefine

module FADSU2 (A0, A1, B0, B1, BCI, CON, BCO, S0, S1);
input  A0, A1, B0, B1, BCI, CON;
output BCO, S0, S1;


and INST10 (I3, BCI, I9);
and INST11 (I4, A0, BCI);
or INST12 (I6, I3, I4, I5);
xor INST13 (S0, A0, I9, BCI);
xnor INST14 (I9, CON, B0);

and INST2 (I5, I9, A0);
and INST30 (I27, I23, A1);
and INST31 (I25, I6, I23);
and INST32 (I26, A1, I6);
or INST33 (BCO, I25, I26, I27);
xor INST34 (S1, A1, I23, I6);
xnor INST35 (I23, CON, B1);


endmodule 

`endcelldefine