spram32x8.v

简单的8位CPU

/* Verilog netlist generated by SCUBA ispLever_v50_Production_Build (40) */
/* C:\ispTOOLS5_0\ispfpga\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch mg5g00 -type sspram -addr_width 5 -num_rows 32 -data_width 8 -outData UNREGISTERED  */
/* Mon May 16 11:34:12 2005 */


`timescale 1 ns / 1 ps
module spram32x8 (Address, Data, Clock, WE, ClockEn, Q);
    input [4:0] Address;
    input [7:0] Data;
    input Clock;
    input WE;
    input ClockEn;
    output [7:0] Q;


    INV INV_addr4 (.A(Address[4]), .Z(addr4_inv));

    AND3 AND3_1 (.A(WE), .B(ClockEn), .C(addr4_inv), .Z(dec_wre3));

    AND3 AND3_0 (.A(WE), .B(ClockEn), .C(Address[4]), .Z(dec_wre7));

    MUX21 mux_7 (.D0(mdL0_0_0), .D1(mdL0_1_0), .SD(Address[4]), .Z(Q[7]));

    MUX21 mux_6 (.D0(mdL0_0_1), .D1(mdL0_1_1), .SD(Address[4]), .Z(Q[6]));

    MUX21 mux_5 (.D0(mdL0_0_2), .D1(mdL0_1_2), .SD(Address[4]), .Z(Q[5]));

    MUX21 mux_4 (.D0(mdL0_0_3), .D1(mdL0_1_3), .SD(Address[4]), .Z(Q[4]));

    MUX21 mux_3 (.D0(mdL0_0_4), .D1(mdL0_1_4), .SD(Address[4]), .Z(Q[3]));

    MUX21 mux_2 (.D0(mdL0_0_5), .D1(mdL0_1_5), .SD(Address[4]), .Z(Q[2]));

    MUX21 mux_1 (.D0(mdL0_0_6), .D1(mdL0_1_6), .SD(Address[4]), .Z(Q[1]));

    MUX21 mux_0 (.D0(mdL0_0_7), .D1(mdL0_1_7), .SD(Address[4]), .Z(Q[0]));

    // synopsys translate_off
    defparam mem_0_0.initval =  64'h0000000000000000;
    // synopsys translate_on
    SPR16X2B mem_0_0 (.DI0(Data[6]), .DI1(Data[7]), .CK(Clock), .WRE(dec_wre3), 
        .AD0(Address[0]), .AD1(Address[1]), .AD2(Address[2]), .AD3(Address[3]), 
        .DO0(mdL0_0_1), .DO1(mdL0_0_0))
             /* synthesis initval="0x0000000000000000" */;

    // synopsys translate_off
    defparam mem_0_1.initval =  64'h0000000000000000;
    // synopsys translate_on
    SPR16X2B mem_0_1 (.DI0(Data[4]), .DI1(Data[5]), .CK(Clock), .WRE(dec_wre3), 
        .AD0(Address[0]), .AD1(Address[1]), .AD2(Address[2]), .AD3(Address[3]), 
        .DO0(mdL0_0_3), .DO1(mdL0_0_2))
             /* synthesis initval="0x0000000000000000" */;

    // synopsys translate_off
    defparam mem_0_2.initval =  64'h0000000000000000;
    // synopsys translate_on
    SPR16X2B mem_0_2 (.DI0(Data[2]), .DI1(Data[3]), .CK(Clock), .WRE(dec_wre3), 
        .AD0(Address[0]), .AD1(Address[1]), .AD2(Address[2]), .AD3(Address[3]), 
        .DO0(mdL0_0_5), .DO1(mdL0_0_4))
             /* synthesis initval="0x0000000000000000" */;

    // synopsys translate_off
    defparam mem_0_3.initval =  64'h0000000000000000;
    // synopsys translate_on
    SPR16X2B mem_0_3 (.DI0(Data[0]), .DI1(Data[1]), .CK(Clock), .WRE(dec_wre3), 
        .AD0(Address[0]), .AD1(Address[1]), .AD2(Address[2]), .AD3(Address[3]), 
        .DO0(mdL0_0_7), .DO1(mdL0_0_6))
             /* synthesis initval="0x0000000000000000" */;

    // synopsys translate_off
    defparam mem_1_0.initval =  64'h0000000000000000;
    // synopsys translate_on
    SPR16X2B mem_1_0 (.DI0(Data[6]), .DI1(Data[7]), .CK(Clock), .WRE(dec_wre7), 
        .AD0(Address[0]), .AD1(Address[1]), .AD2(Address[2]), .AD3(Address[3]), 
        .DO0(mdL0_1_1), .DO1(mdL0_1_0))
             /* synthesis initval="0x0000000000000000" */;

    // synopsys translate_off
    defparam mem_1_1.initval =  64'h0000000000000000;
    // synopsys translate_on
    SPR16X2B mem_1_1 (.DI0(Data[4]), .DI1(Data[5]), .CK(Clock), .WRE(dec_wre7), 
        .AD0(Address[0]), .AD1(Address[1]), .AD2(Address[2]), .AD3(Address[3]), 
        .DO0(mdL0_1_3), .DO1(mdL0_1_2))
             /* synthesis initval="0x0000000000000000" */;

    // synopsys translate_off
    defparam mem_1_2.initval =  64'h0000000000000000;
    // synopsys translate_on
    SPR16X2B mem_1_2 (.DI0(Data[2]), .DI1(Data[3]), .CK(Clock), .WRE(dec_wre7), 
        .AD0(Address[0]), .AD1(Address[1]), .AD2(Address[2]), .AD3(Address[3]), 
        .DO0(mdL0_1_5), .DO1(mdL0_1_4))
             /* synthesis initval="0x0000000000000000" */;

    // synopsys translate_off
    defparam mem_1_3.initval =  64'h0000000000000000;
    // synopsys translate_on
    SPR16X2B mem_1_3 (.DI0(Data[0]), .DI1(Data[1]), .CK(Clock), .WRE(dec_wre7), 
        .AD0(Address[0]), .AD1(Address[1]), .AD2(Address[2]), .AD3(Address[3]), 
        .DO0(mdL0_1_7), .DO1(mdL0_1_6))
             /* synthesis initval="0x0000000000000000" */;



    // exemplar begin
    // exemplar attribute mem_0_0 initval 0x0000000000000000
    // exemplar attribute mem_0_1 initval 0x0000000000000000
    // exemplar attribute mem_0_2 initval 0x0000000000000000
    // exemplar attribute mem_0_3 initval 0x0000000000000000
    // exemplar attribute mem_1_0 initval 0x0000000000000000
    // exemplar attribute mem_1_1 initval 0x0000000000000000
    // exemplar attribute mem_1_2 initval 0x0000000000000000
    // exemplar attribute mem_1_3 initval 0x0000000000000000
    // exemplar end

endmodule