uart.hier_info

FPGA-UART异步通信串行口设计实例

enable => dffs[3].ENA
enable => dffs[2].ENA
enable => dffs[1].ENA
enable => dffs[0].ENA
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
sconst => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffs[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffs[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffs[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffs[4].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= shiftout~0.DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|lpm_dff:$00005
clock => dffs[7].CLK
clock => dffs[6].CLK
clock => dffs[5].CLK
clock => dffs[4].CLK
clock => dffs[3].CLK
clock => dffs[2].CLK
clock => dffs[1].CLK
clock => dffs[0].CLK
enable => dffs[7].ENA
enable => dffs[6].ENA
enable => dffs[5].ENA
enable => dffs[4].ENA
enable => dffs[3].ENA
enable => dffs[2].ENA
enable => dffs[1].ENA
enable => dffs[0].ENA
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
sconst => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffs[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffs[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffs[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffs[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffs[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffs[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffs[7].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= shiftout~0.DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|clk_pdiv:$00007
CLK => lpm_dff:$00004.clock
CLK => lpm_counter:$00002.clock
D[0] => lpm_compare:$00000.datab[0]
D[1] => lpm_compare:$00000.datab[1]
D[2] => lpm_compare:$00000.datab[2]
D[3] => lpm_compare:$00000.datab[3]
D[4] => lpm_compare:$00000.datab[4]
D[5] => lpm_compare:$00000.datab[5]
D[6] => lpm_compare:$00000.datab[6]
D[7] => lpm_compare:$00000.datab[7]
D[8] => lpm_compare:$00000.datab[8]
D[9] => lpm_compare:$00000.datab[9]
D[10] => lpm_compare:$00000.datab[10]
D[11] => lpm_compare:$00000.datab[11]
D[12] => lpm_compare:$00000.datab[12]
D[13] => lpm_compare:$00000.datab[13]
D[14] => lpm_compare:$00000.datab[14]
D[15] => lpm_compare:$00000.datab[15]
D[16] => lpm_compare:$00000.datab[16]
enable => lpm_dff:$00004.enable
enable => lpm_counter:$00002.clk_en
RESET => lpm_counter:$00002.aclr
OUT <= lpm_dff:$00004.q[0]
q[0] <= lpm_counter:$00002.q[0]
q[1] <= lpm_counter:$00002.q[1]
q[2] <= lpm_counter:$00002.q[2]
q[3] <= lpm_counter:$00002.q[3]
q[4] <= lpm_counter:$00002.q[4]
q[5] <= lpm_counter:$00002.q[5]
q[6] <= lpm_counter:$00002.q[6]
q[7] <= lpm_counter:$00002.q[7]
q[8] <= lpm_counter:$00002.q[8]
q[9] <= lpm_counter:$00002.q[9]
q[10] <= lpm_counter:$00002.q[10]
q[11] <= lpm_counter:$00002.q[11]
q[12] <= lpm_counter:$00002.q[12]
q[13] <= lpm_counter:$00002.q[13]
q[14] <= lpm_counter:$00002.q[14]
q[15] <= lpm_counter:$00002.q[15]
q[16] <= lpm_counter:$00002.q[16]


|uart|Rx:4|clk_pdiv:$00007|lpm_compare:$00000
dataa[0] => cmpr_ied:auto_generated.dataa[0]
dataa[1] => cmpr_ied:auto_generated.dataa[1]
dataa[2] => cmpr_ied:auto_generated.dataa[2]
dataa[3] => cmpr_ied:auto_generated.dataa[3]
dataa[4] => cmpr_ied:auto_generated.dataa[4]
dataa[5] => cmpr_ied:auto_generated.dataa[5]
dataa[6] => cmpr_ied:auto_generated.dataa[6]
dataa[7] => cmpr_ied:auto_generated.dataa[7]
dataa[8] => cmpr_ied:auto_generated.dataa[8]
dataa[9] => cmpr_ied:auto_generated.dataa[9]
dataa[10] => cmpr_ied:auto_generated.dataa[10]
dataa[11] => cmpr_ied:auto_generated.dataa[11]
dataa[12] => cmpr_ied:auto_generated.dataa[12]
dataa[13] => cmpr_ied:auto_generated.dataa[13]
dataa[14] => cmpr_ied:auto_generated.dataa[14]
dataa[15] => cmpr_ied:auto_generated.dataa[15]
dataa[16] => cmpr_ied:auto_generated.dataa[16]
datab[0] => cmpr_ied:auto_generated.datab[0]
datab[1] => cmpr_ied:auto_generated.datab[1]
datab[2] => cmpr_ied:auto_generated.datab[2]
datab[3] => cmpr_ied:auto_generated.datab[3]
datab[4] => cmpr_ied:auto_generated.datab[4]
datab[5] => cmpr_ied:auto_generated.datab[5]
datab[6] => cmpr_ied:auto_generated.datab[6]
datab[7] => cmpr_ied:auto_generated.datab[7]
datab[8] => cmpr_ied:auto_generated.datab[8]
datab[9] => cmpr_ied:auto_generated.datab[9]
datab[10] => cmpr_ied:auto_generated.datab[10]
datab[11] => cmpr_ied:auto_generated.datab[11]
datab[12] => cmpr_ied:auto_generated.datab[12]
datab[13] => cmpr_ied:auto_generated.datab[13]
datab[14] => cmpr_ied:auto_generated.datab[14]
datab[15] => cmpr_ied:auto_generated.datab[15]
datab[16] => cmpr_ied:auto_generated.datab[16]
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
alb <= <GND>
aeb <= cmpr_ied:auto_generated.aeb
agb <= <GND>
aleb <= <GND>
aneb <= <GND>
ageb <= <GND>


|uart|Rx:4|clk_pdiv:$00007|lpm_compare:$00000|cmpr_ied:auto_generated
aeb <= aeb_int.DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|clk_pdiv:$00007|lpm_counter:$00002
clock => cntr_d8h:auto_generated.clock
clk_en => cntr_d8h:auto_generated.clk_en
cnt_en => ~NO_FANOUT~
updown => ~NO_FANOUT~
aclr => cntr_d8h:auto_generated.aclr
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => cntr_d8h:auto_generated.sclr
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
data[5] => ~NO_FANOUT~
data[6] => ~NO_FANOUT~
data[7] => ~NO_FANOUT~
data[8] => ~NO_FANOUT~
data[9] => ~NO_FANOUT~
data[10] => ~NO_FANOUT~
data[11] => ~NO_FANOUT~
data[12] => ~NO_FANOUT~
data[13] => ~NO_FANOUT~
data[14] => ~NO_FANOUT~
data[15] => ~NO_FANOUT~
data[16] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_d8h:auto_generated.q[0]
q[1] <= cntr_d8h:auto_generated.q[1]
q[2] <= cntr_d8h:auto_generated.q[2]
q[3] <= cntr_d8h:auto_generated.q[3]
q[4] <= cntr_d8h:auto_generated.q[4]
q[5] <= cntr_d8h:auto_generated.q[5]
q[6] <= cntr_d8h:auto_generated.q[6]
q[7] <= cntr_d8h:auto_generated.q[7]
q[8] <= cntr_d8h:auto_generated.q[8]
q[9] <= cntr_d8h:auto_generated.q[9]
q[10] <= cntr_d8h:auto_generated.q[10]
q[11] <= cntr_d8h:auto_generated.q[11]
q[12] <= cntr_d8h:auto_generated.q[12]
q[13] <= cntr_d8h:auto_generated.q[13]
q[14] <= cntr_d8h:auto_generated.q[14]
q[15] <= cntr_d8h:auto_generated.q[15]
q[16] <= cntr_d8h:auto_generated.q[16]
cout <= <GND>
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|uart|Rx:4|clk_pdiv:$00007|lpm_counter:$00002|cntr_d8h:auto_generated
aclr => counter_cella0.ACLR
aclr => counter_cella1.ACLR
aclr => counter_cella2.ACLR
aclr => counter_cella3.ACLR
aclr => counter_cella4.ACLR
aclr => counter_cella5.ACLR
aclr => counter_cella6.ACLR
aclr => counter_cella7.ACLR
aclr => counter_cella8.ACLR
aclr => counter_cella9.ACLR
aclr => counter_cella10.ACLR
aclr => counter_cella11.ACLR
aclr => counter_cella12.ACLR
aclr => counter_cella13.ACLR
aclr => counter_cella14.ACLR
aclr => counter_cella15.ACLR
aclr => counter_cella16.ACLR
clk_en => counter_cella0.ENA
clk_en => counter_cella1.ENA
clk_en => counter_cella2.ENA
clk_en => counter_cella3.ENA
clk_en => counter_cella4.ENA
clk_en => counter_cella5.ENA
clk_en => counter_cella6.ENA
clk_en => counter_cella7.ENA
clk_en => counter_cella8.ENA
clk_en => counter_cella9.ENA
clk_en => counter_cella10.ENA
clk_en => counter_cella11.ENA
clk_en => counter_cella12.ENA
clk_en => counter_cella13.ENA
clk_en => counter_cella14.ENA
clk_en => counter_cella15.ENA
clk_en => counter_cella16.ENA
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
clock => counter_cella7.CLK
clock => counter_cella8.CLK
clock => counter_cella9.CLK
clock => counter_cella10.CLK
clock => counter_cella11.CLK
clock => counter_cella12.CLK
clock => counter_cella13.CLK
clock => counter_cella14.CLK
clock => counter_cella15.CLK
clock => counter_cella16.CLK
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
q[5] <= counter_cella5.REGOUT
q[6] <= counter_cella6.REGOUT
q[7] <= counter_cella7.REGOUT
q[8] <= counter_cella8.REGOUT
q[9] <= counter_cella9.REGOUT
q[10] <= counter_cella10.REGOUT
q[11] <= counter_cella11.REGOUT
q[12] <= counter_cella12.REGOUT
q[13] <= counter_cella13.REGOUT
q[14] <= counter_cella14.REGOUT
q[15] <= counter_cella15.REGOUT
q[16] <= counter_cella16.REGOUT
sclr => counter_cella0.SCLR
sclr => counter_cella1.SCLR
sclr => counter_cella2.SCLR
sclr => counter_cella3.SCLR
sclr => counter_cella4.SCLR
sclr => counter_cella5.SCLR
sclr => counter_cella6.SCLR
sclr => counter_cella7.SCLR
sclr => counter_cella8.SCLR
sclr => counter_cella9.SCLR
sclr => counter_cella10.SCLR
sclr => counter_cella11.SCLR
sclr => counter_cella12.SCLR
sclr => counter_cella13.SCLR
sclr => counter_cella14.SCLR
sclr => counter_cella15.SCLR
sclr => counter_cella16.SCLR


|uart|Rx:4|clk_pdiv:$00007|lpm_dff:$00004
clock => dffs[0].CLK
enable => dffs[0].ENA
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
sconst => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= shiftout~0.DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|lpm_dff:$00009
clock => dffs[0].CLK
enable => dffs[0].ENA
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
sconst => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= shiftout~0.DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|Filterx:$00011
clk => filt_tpl:$00000.clk
S_IN[0] => filt_tpl:$00000.f_in
reset => filt_tpl:$00000.reset
preset => filt_tpl:$00000.preset
S_OUT[0] <= F_ARRAY[0].DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|Filterx:$00011|filt_tpl:$00000
CLK => FF[2].CLK
CLK => FF[1].CLK
CLK => FF[0].CLK
CLK => SYNC.CLK
F_IN => FF[0].DATAIN
F_OUT <= SYNC.DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|lpm_counter:$00013
clock => cntr_5og:auto_generated.clock
clk_en => cntr_5og:auto_generated.clk_en
cnt_en => ~NO_FANOUT~
updown => ~NO_FANOUT~
aclr => cntr_5og:auto_generated.aclr
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_5og:auto_generated.q[0]
q[1] <= cntr_5og:auto_generated.q[1]
q[2] <= cntr_5og:auto_generated.q[2]
q[3] <= cntr_5og:auto_generated.q[3]
cout <= <GND>
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|uart|Rx:4|lpm_counter:$00013|cntr_5og:auto_generated
aclr => counter_cella0.ACLR
aclr => counter_cella1.ACLR
aclr => counter_cella2.ACLR
aclr => counter_cella3.ACLR
clk_en => counter_cella0.ENA
clk_en => counter_cella1.ENA
clk_en => counter_cella2.ENA
clk_en => counter_cella3.ENA
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT


|uart|Rx:4|Par_Gen:$00015
D[0] => OUT[1].IN0
D[1] => OUT[1].IN1
D[2] => OUT[2].IN1
D[3] => OUT[3].IN1
D[4] => OUT[4].IN1
D[5] => OUT[5].IN1
D[6] => OUT[6].IN1
D[7] => OUT[7].IN1
ODD/EVEN <= OUT[7].DB_MAX_OUTPUT_PORT_TYPE