uart.hier_info

FPGA-UART异步通信串行口设计实例

aclr => cntr_d8h:auto_generated.aclr
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => cntr_d8h:auto_generated.sclr
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
data[5] => ~NO_FANOUT~
data[6] => ~NO_FANOUT~
data[7] => ~NO_FANOUT~
data[8] => ~NO_FANOUT~
data[9] => ~NO_FANOUT~
data[10] => ~NO_FANOUT~
data[11] => ~NO_FANOUT~
data[12] => ~NO_FANOUT~
data[13] => ~NO_FANOUT~
data[14] => ~NO_FANOUT~
data[15] => ~NO_FANOUT~
data[16] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_d8h:auto_generated.q[0]
q[1] <= cntr_d8h:auto_generated.q[1]
q[2] <= cntr_d8h:auto_generated.q[2]
q[3] <= cntr_d8h:auto_generated.q[3]
q[4] <= cntr_d8h:auto_generated.q[4]
q[5] <= cntr_d8h:auto_generated.q[5]
q[6] <= cntr_d8h:auto_generated.q[6]
q[7] <= cntr_d8h:auto_generated.q[7]
q[8] <= cntr_d8h:auto_generated.q[8]
q[9] <= cntr_d8h:auto_generated.q[9]
q[10] <= cntr_d8h:auto_generated.q[10]
q[11] <= cntr_d8h:auto_generated.q[11]
q[12] <= cntr_d8h:auto_generated.q[12]
q[13] <= cntr_d8h:auto_generated.q[13]
q[14] <= cntr_d8h:auto_generated.q[14]
q[15] <= cntr_d8h:auto_generated.q[15]
q[16] <= cntr_d8h:auto_generated.q[16]
cout <= <GND>
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|uart|TX:5|clk_pdiv:$00001|lpm_counter:$00002|cntr_d8h:auto_generated
aclr => counter_cella0.ACLR
aclr => counter_cella1.ACLR
aclr => counter_cella2.ACLR
aclr => counter_cella3.ACLR
aclr => counter_cella4.ACLR
aclr => counter_cella5.ACLR
aclr => counter_cella6.ACLR
aclr => counter_cella7.ACLR
aclr => counter_cella8.ACLR
aclr => counter_cella9.ACLR
aclr => counter_cella10.ACLR
aclr => counter_cella11.ACLR
aclr => counter_cella12.ACLR
aclr => counter_cella13.ACLR
aclr => counter_cella14.ACLR
aclr => counter_cella15.ACLR
aclr => counter_cella16.ACLR
clk_en => counter_cella0.ENA
clk_en => counter_cella1.ENA
clk_en => counter_cella2.ENA
clk_en => counter_cella3.ENA
clk_en => counter_cella4.ENA
clk_en => counter_cella5.ENA
clk_en => counter_cella6.ENA
clk_en => counter_cella7.ENA
clk_en => counter_cella8.ENA
clk_en => counter_cella9.ENA
clk_en => counter_cella10.ENA
clk_en => counter_cella11.ENA
clk_en => counter_cella12.ENA
clk_en => counter_cella13.ENA
clk_en => counter_cella14.ENA
clk_en => counter_cella15.ENA
clk_en => counter_cella16.ENA
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
clock => counter_cella7.CLK
clock => counter_cella8.CLK
clock => counter_cella9.CLK
clock => counter_cella10.CLK
clock => counter_cella11.CLK
clock => counter_cella12.CLK
clock => counter_cella13.CLK
clock => counter_cella14.CLK
clock => counter_cella15.CLK
clock => counter_cella16.CLK
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
q[5] <= counter_cella5.REGOUT
q[6] <= counter_cella6.REGOUT
q[7] <= counter_cella7.REGOUT
q[8] <= counter_cella8.REGOUT
q[9] <= counter_cella9.REGOUT
q[10] <= counter_cella10.REGOUT
q[11] <= counter_cella11.REGOUT
q[12] <= counter_cella12.REGOUT
q[13] <= counter_cella13.REGOUT
q[14] <= counter_cella14.REGOUT
q[15] <= counter_cella15.REGOUT
q[16] <= counter_cella16.REGOUT
sclr => counter_cella0.SCLR
sclr => counter_cella1.SCLR
sclr => counter_cella2.SCLR
sclr => counter_cella3.SCLR
sclr => counter_cella4.SCLR
sclr => counter_cella5.SCLR
sclr => counter_cella6.SCLR
sclr => counter_cella7.SCLR
sclr => counter_cella8.SCLR
sclr => counter_cella9.SCLR
sclr => counter_cella10.SCLR
sclr => counter_cella11.SCLR
sclr => counter_cella12.SCLR
sclr => counter_cella13.SCLR
sclr => counter_cella14.SCLR
sclr => counter_cella15.SCLR
sclr => counter_cella16.SCLR


|uart|TX:5|clk_pdiv:$00001|lpm_dff:$00004
clock => dffs[0].CLK
enable => dffs[0].ENA
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
sconst => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= shiftout~0.DB_MAX_OUTPUT_PORT_TYPE


|uart|TX:5|lpm_dff:$00003
clock => dffs[0].CLK
enable => dffs[0].ENA
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
sconst => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= shiftout~0.DB_MAX_OUTPUT_PORT_TYPE


|uart|TX:5|lpm_dff:$00005
clock => dffs[0].CLK
enable => dffs[0].ENA
aconst => ~NO_FANOUT~
sconst => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= shiftout~0.DB_MAX_OUTPUT_PORT_TYPE


|uart|TX:5|ShiftReg:$00007
CLK => FF[7].CLK
CLK => FF[6].CLK
CLK => FF[5].CLK
CLK => FF[4].CLK
CLK => FF[3].CLK
CLK => FF[2].CLK
CLK => FF[1].CLK
CLK => FF[0].CLK
ENABLE => FF[7].ENA
ENABLE => FF[6].ENA
ENABLE => FF[5].ENA
ENABLE => FF[4].ENA
ENABLE => FF[3].ENA
ENABLE => FF[2].ENA
ENABLE => FF[1].ENA
ENABLE => FF[0].ENA
DIN => FF[7].DATAIN
Q[0] <= FF[0].DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= FF[1].DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= FF[2].DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= FF[3].DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= FF[4].DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= FF[5].DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= FF[6].DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= FF[7].DB_MAX_OUTPUT_PORT_TYPE
DOUT <= FF[0].DB_MAX_OUTPUT_PORT_TYPE


|uart|TX:5|lpm_mux:$00009
data[0][0] => mux_6fc:auto_generated.data[0]
data[1][0] => mux_6fc:auto_generated.data[1]
data[2][0] => mux_6fc:auto_generated.data[2]
data[3][0] => mux_6fc:auto_generated.data[3]
sel[0] => mux_6fc:auto_generated.sel[0]
sel[1] => mux_6fc:auto_generated.sel[1]
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= mux_6fc:auto_generated.result[0]


|uart|TX:5|lpm_mux:$00009|mux_6fc:auto_generated
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE


|uart|TX:5|lpm_counter:$00011
clock => cntr_0gi:auto_generated.clock
clk_en => ~NO_FANOUT~
cnt_en => cntr_0gi:auto_generated.cnt_en
updown => ~NO_FANOUT~
aclr => cntr_0gi:auto_generated.aclr
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_0gi:auto_generated.q[0]
q[1] <= cntr_0gi:auto_generated.q[1]
q[2] <= cntr_0gi:auto_generated.q[2]
q[3] <= cntr_0gi:auto_generated.q[3]
q[4] <= cntr_0gi:auto_generated.q[4]
cout <= <GND>
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|uart|TX:5|lpm_counter:$00011|cntr_0gi:auto_generated
aclr => counter_cella0.ACLR
aclr => counter_cella1.ACLR
aclr => counter_cella2.ACLR
aclr => counter_cella3.ACLR
aclr => counter_cella4.ACLR
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
cnt_en => counter_cella0.DATAB
cnt_en => counter_cella1.DATAB
cnt_en => counter_cella2.DATAB
cnt_en => counter_cella3.DATAB
cnt_en => counter_cella4.DATAB
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT


|uart|TX:5|Par_Gen:$00013
D[0] => OUT[1].IN0
D[1] => OUT[1].IN1
D[2] => OUT[2].IN1
D[3] => OUT[3].IN1
D[4] => OUT[4].IN1
D[5] => OUT[5].IN1
D[6] => OUT[6].IN1
D[7] => OUT[7].IN1
ODD/EVEN <= OUT[7].DB_MAX_OUTPUT_PORT_TYPE


|uart|TX:5|lpm_dff:$00015
clock => dffs[0].CLK
enable => dffs[0].ENA
aconst => ~NO_FANOUT~
sconst => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= shiftout~0.DB_MAX_OUTPUT_PORT_TYPE


|uart|TX:5|lpm_dff:$00017
clock => dffs[0].CLK
enable => dffs[0].ENA
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
sconst => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= shiftout~0.DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4
clk => lpm_counter:$00013.clock
clk => filterx:$00011.clk
clk => clk_pdiv:$00007.clk
clk => lpm_dff:$00005.clock
clk => lpm_dff:$00003.clock
clk => lpm_dff:$00001.clock
clk => Rxss~0.IN1
reset => filterx:$00011.preset
reset => lpm_dff:$00001.aclr
reset => Rxss~2.IN1
CfgReg[6] => ~NO_FANOUT~
DIVISOR[0] => clk_pdiv:$00007.d[0]
DIVISOR[1] => clk_pdiv:$00007.d[1]
DIVISOR[2] => clk_pdiv:$00007.d[2]
DIVISOR[3] => clk_pdiv:$00007.d[3]
DIVISOR[4] => clk_pdiv:$00007.d[4]
DIVISOR[5] => clk_pdiv:$00007.d[5]
DIVISOR[6] => clk_pdiv:$00007.d[6]
DIVISOR[7] => clk_pdiv:$00007.d[7]
DIVISOR[8] => clk_pdiv:$00007.d[8]
DIVISOR[9] => clk_pdiv:$00007.d[9]
DIVISOR[10] => clk_pdiv:$00007.d[10]
DIVISOR[11] => clk_pdiv:$00007.d[11]
DIVISOR[12] => clk_pdiv:$00007.d[12]
DIVISOR[13] => clk_pdiv:$00007.d[13]
DIVISOR[14] => clk_pdiv:$00007.d[14]
DIVISOR[15] => clk_pdiv:$00007.d[15]
DIVISOR[16] => clk_pdiv:$00007.d[16]
RxEND <= RxEND~0.DB_MAX_OUTPUT_PORT_TYPE
RxReg[0] <= lpm_dff:$00001.q[0]
RxReg[1] <= lpm_dff:$00001.q[1]
RxReg[2] <= lpm_dff:$00001.q[2]
RxReg[3] <= lpm_dff:$00001.q[3]
RxReg[4] <= lpm_dff:$00001.q[4]
RxReg[5] <= lpm_dff:$00001.q[5]
RxReg[6] <= lpm_dff:$00001.q[6]
RxReg[7] <= lpm_dff:$00001.q[7]
RxStatus[0] <= RxStatus$wire[0].DB_MAX_OUTPUT_PORT_TYPE
RxStatus[1] <= RxStatus$wire[1].DB_MAX_OUTPUT_PORT_TYPE
RxStatus[2] <= RxStatus$wire[2].DB_MAX_OUTPUT_PORT_TYPE
RxStatus[3] <= RxStatus$wire[3].DB_MAX_OUTPUT_PORT_TYPE
RxStatus[4] <= RxStatus$wire[4].DB_MAX_OUTPUT_PORT_TYPE
Rx => filterx:$00011.s_in[0]


|uart|Rx:4|lpm_dff:$00001
clock => dffs[7].CLK
clock => dffs[6].CLK
clock => dffs[5].CLK
clock => dffs[4].CLK
clock => dffs[3].CLK
clock => dffs[2].CLK
clock => dffs[1].CLK
clock => dffs[0].CLK
enable => dffs[7].ENA
enable => dffs[6].ENA
enable => dffs[5].ENA
enable => dffs[4].ENA
enable => dffs[3].ENA
enable => dffs[2].ENA
enable => dffs[1].ENA
enable => dffs[0].ENA
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
sconst => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffs[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffs[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffs[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffs[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffs[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffs[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffs[7].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= shiftout~0.DB_MAX_OUTPUT_PORT_TYPE


|uart|Rx:4|lpm_dff:$00003
clock => dffs[4].CLK
clock => dffs[3].CLK
clock => dffs[2].CLK
clock => dffs[1].CLK
clock => dffs[0].CLK
enable => dffs[4].ENA