uart.hier_info

FPGA-UART异步通信串行口设计实例

|uart
RCVD <= UARTCTRL:inst3.RCVD
CLK => UARTCTRL:inst3.CLK
RESET => UARTCTRL:inst3.RESET
Rx => Rx:4.Rx
Di[0] => UARTCTRL:inst3.Di[0]
Di[1] => UARTCTRL:inst3.Di[1]
Di[2] => UARTCTRL:inst3.Di[2]
Di[3] => UARTCTRL:inst3.Di[3]
Di[4] => UARTCTRL:inst3.Di[4]
Di[5] => UARTCTRL:inst3.Di[5]
Di[6] => UARTCTRL:inst3.Di[6]
Di[7] => UARTCTRL:inst3.Di[7]
SENT <= UARTCTRL:inst3.SENT
INT <= UARTCTRL:inst3.INT
Tx <= TX:5.TX
Do[0] <= UARTCTRL:inst3.Do[0]
Do[1] <= UARTCTRL:inst3.Do[1]
Do[2] <= UARTCTRL:inst3.Do[2]
Do[3] <= UARTCTRL:inst3.Do[3]
Do[4] <= UARTCTRL:inst3.Do[4]
Do[5] <= UARTCTRL:inst3.Do[5]
Do[6] <= UARTCTRL:inst3.Do[6]
Do[7] <= UARTCTRL:inst3.Do[7]
XOUT[0] <= TX:5.XOUT[0]
XOUT[1] <= TX:5.XOUT[1]
XOUT[2] <= TX:5.XOUT[2]
XOUT[3] <= TX:5.XOUT[3]


|uart|UARTCTRL:inst3
Di[0] => lpm_dff:$00012.data[0]
Di[1] => lpm_dff:$00012.data[1]
Di[2] => lpm_dff:$00012.data[2]
Di[3] => lpm_dff:$00012.data[3]
Di[4] => lpm_dff:$00012.data[4]
Di[5] => lpm_dff:$00012.data[5]
Di[6] => lpm_dff:$00012.data[6]
Di[7] => lpm_dff:$00012.data[7]
Do[0] <= DOMUX[0].DB_MAX_OUTPUT_PORT_TYPE
Do[1] <= DOMUX[1].DB_MAX_OUTPUT_PORT_TYPE
Do[2] <= DOMUX[2].DB_MAX_OUTPUT_PORT_TYPE
Do[3] <= DOMUX[3].DB_MAX_OUTPUT_PORT_TYPE
Do[4] <= DOMUX[4].DB_MAX_OUTPUT_PORT_TYPE
Do[5] <= DOMUX[5].DB_MAX_OUTPUT_PORT_TYPE
Do[6] <= DOMUX[6].DB_MAX_OUTPUT_PORT_TYPE
Do[7] <= DOMUX[7].DB_MAX_OUTPUT_PORT_TYPE
CLK => RxCLK.DATAIN
CLK => TxCLK.DATAIN
CLK => lpm_dff:$00020.clock
CLK => lpm_dff:$00018.clock
CLK => lpm_dff:$00016.clock
CLK => RxRdss~0.IN1
CLK => TxWrss~0.IN1
RESET => RxReset.DATAIN
RESET => TxReset.DATAIN
RESET => lpm_dff:$00020.aclr
RESET => lpm_dff:$00018.aclr
RESET => lpm_dff:$00016.aclr
RESET => lpm_dff:$00012.aclr
RESET => RxRdss~2.IN1
RESET => TxWrss~2.IN1
A[0] => lpm_mux:$00014.sel[0]
A[1] => lpm_mux:$00014.sel[1]
INT <= lpm_dff:$00020.q[0]
RCVD <= lpm_dff:$00016.q[0]
SENT <= lpm_dff:$00018.q[0]
TxDIVISOR[0] <= DIVd[0].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[1] <= DIVd[1].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[2] <= DIVd[2].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[3] <= DIVd[3].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[4] <= DIVd[4].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[5] <= DIVd[5].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[6] <= DIVd[6].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[7] <= DIVd[7].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[8] <= DIVd[8].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[9] <= DIVd[9].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[10] <= DIVd[10].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[11] <= DIVd[11].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[12] <= DIVd[12].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[13] <= DIVd[13].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[14] <= DIVd[14].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[15] <= DIVd[15].DB_MAX_OUTPUT_PORT_TYPE
TxDIVISOR[16] <= DIVd[16].DB_MAX_OUTPUT_PORT_TYPE
TxCfgReg[0] <= CfgReg[0].DB_MAX_OUTPUT_PORT_TYPE
TxCfgReg[1] <= CfgReg[1].DB_MAX_OUTPUT_PORT_TYPE
TxCfgReg[2] <= CfgReg[2].DB_MAX_OUTPUT_PORT_TYPE
TxCfgReg[3] <= CfgReg[3].DB_MAX_OUTPUT_PORT_TYPE
TxCfgReg[4] <= CfgReg[4].DB_MAX_OUTPUT_PORT_TYPE
TxCfgReg[5] <= CfgReg[5].DB_MAX_OUTPUT_PORT_TYPE
TxCfgReg[6] <= CfgReg[6].DB_MAX_OUTPUT_PORT_TYPE
TxReg[0] <= lpm_dff:$00012.q[0]
TxReg[1] <= lpm_dff:$00012.q[1]
TxReg[2] <= lpm_dff:$00012.q[2]
TxReg[3] <= lpm_dff:$00012.q[3]
TxReg[4] <= lpm_dff:$00012.q[4]
TxReg[5] <= lpm_dff:$00012.q[5]
TxReg[6] <= lpm_dff:$00012.q[6]
TxReg[7] <= lpm_dff:$00012.q[7]
TxSTATUS => lpm_mux:$00014.data[1][0]
TxEnd => lpm_dff:$00018.data[0]
TxStart <= TxWr2.DB_MAX_OUTPUT_PORT_TYPE
TxReset <= RESET.DB_MAX_OUTPUT_PORT_TYPE
TxCLK <= CLK.DB_MAX_OUTPUT_PORT_TYPE
RxSTATUS[0] => lpm_mux:$00014.data[1][1]
RxSTATUS[1] => lpm_mux:$00014.data[1][2]
RxSTATUS[2] => lpm_mux:$00014.data[1][3]
RxSTATUS[3] => lpm_mux:$00014.data[1][4]
RxSTATUS[4] => lpm_mux:$00014.data[1][5]
RxReg[0] => lpm_mux:$00014.data[0][0]
RxReg[1] => lpm_mux:$00014.data[0][1]
RxReg[2] => lpm_mux:$00014.data[0][2]
RxReg[3] => lpm_mux:$00014.data[0][3]
RxReg[4] => lpm_mux:$00014.data[0][4]
RxReg[5] => lpm_mux:$00014.data[0][5]
RxReg[6] => lpm_mux:$00014.data[0][6]
RxReg[7] => lpm_mux:$00014.data[0][7]
RxDIVISOR[0] <= DIVd[0].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[1] <= DIVd[1].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[2] <= DIVd[2].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[3] <= DIVd[3].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[4] <= DIVd[4].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[5] <= DIVd[5].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[6] <= DIVd[6].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[7] <= DIVd[7].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[8] <= DIVd[8].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[9] <= DIVd[9].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[10] <= DIVd[10].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[11] <= DIVd[11].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[12] <= DIVd[12].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[13] <= DIVd[13].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[14] <= DIVd[14].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[15] <= DIVd[15].DB_MAX_OUTPUT_PORT_TYPE
RxDIVISOR[16] <= DIVd[16].DB_MAX_OUTPUT_PORT_TYPE
RxCfgReg[0] <= CfgReg[0].DB_MAX_OUTPUT_PORT_TYPE
RxCfgReg[1] <= CfgReg[1].DB_MAX_OUTPUT_PORT_TYPE
RxCfgReg[2] <= CfgReg[2].DB_MAX_OUTPUT_PORT_TYPE
RxCfgReg[3] <= CfgReg[3].DB_MAX_OUTPUT_PORT_TYPE
RxCfgReg[4] <= CfgReg[4].DB_MAX_OUTPUT_PORT_TYPE
RxCfgReg[5] <= CfgReg[5].DB_MAX_OUTPUT_PORT_TYPE
RxCfgReg[6] <= CfgReg[6].DB_MAX_OUTPUT_PORT_TYPE
RxEnd => lpm_dff:$00016.data[0]
RxStart <= RxRd2.DB_MAX_OUTPUT_PORT_TYPE
RxReset <= RESET.DB_MAX_OUTPUT_PORT_TYPE
RxCLK <= CLK.DB_MAX_OUTPUT_PORT_TYPE


|uart|UARTCTRL:inst3|lpm_dff:$00012
clock => dffs[7].CLK
clock => dffs[6].CLK
clock => dffs[5].CLK
clock => dffs[4].CLK
clock => dffs[3].CLK
clock => dffs[2].CLK
clock => dffs[1].CLK
clock => dffs[0].CLK
enable => dffs[7].ENA
enable => dffs[6].ENA
enable => dffs[5].ENA
enable => dffs[4].ENA
enable => dffs[3].ENA
enable => dffs[2].ENA
enable => dffs[1].ENA
enable => dffs[0].ENA
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
sconst => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffs[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffs[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffs[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffs[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffs[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffs[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffs[7].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= shiftout~0.DB_MAX_OUTPUT_PORT_TYPE


|uart|UARTCTRL:inst3|lpm_mux:$00014
data[0][0] => mux_dfc:auto_generated.data[0]
data[0][1] => mux_dfc:auto_generated.data[1]
data[0][2] => mux_dfc:auto_generated.data[2]
data[0][3] => mux_dfc:auto_generated.data[3]
data[0][4] => mux_dfc:auto_generated.data[4]
data[0][5] => mux_dfc:auto_generated.data[5]
data[0][6] => mux_dfc:auto_generated.data[6]
data[0][7] => mux_dfc:auto_generated.data[7]
data[1][0] => mux_dfc:auto_generated.data[8]
data[1][1] => mux_dfc:auto_generated.data[9]
data[1][2] => mux_dfc:auto_generated.data[10]
data[1][3] => mux_dfc:auto_generated.data[11]
data[1][4] => mux_dfc:auto_generated.data[12]
data[1][5] => mux_dfc:auto_generated.data[13]
data[1][6] => mux_dfc:auto_generated.data[14]
data[1][7] => mux_dfc:auto_generated.data[15]
data[2][0] => mux_dfc:auto_generated.data[16]
data[2][1] => mux_dfc:auto_generated.data[17]
data[2][2] => mux_dfc:auto_generated.data[18]
data[2][3] => mux_dfc:auto_generated.data[19]
data[2][4] => mux_dfc:auto_generated.data[20]
data[2][5] => mux_dfc:auto_generated.data[21]
data[2][6] => mux_dfc:auto_generated.data[22]
data[2][7] => mux_dfc:auto_generated.data[23]
data[3][0] => mux_dfc:auto_generated.data[24]
data[3][1] => mux_dfc:auto_generated.data[25]
data[3][2] => mux_dfc:auto_generated.data[26]
data[3][3] => mux_dfc:auto_generated.data[27]
data[3][4] => mux_dfc:auto_generated.data[28]
data[3][5] => mux_dfc:auto_generated.data[29]
data[3][6] => mux_dfc:auto_generated.data[30]
data[3][7] => mux_dfc:auto_generated.data[31]
sel[0] => mux_dfc:auto_generated.sel[0]
sel[1] => mux_dfc:auto_generated.sel[1]
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= mux_dfc:auto_generated.result[0]
result[1] <= mux_dfc:auto_generated.result[1]
result[2] <= mux_dfc:auto_generated.result[2]
result[3] <= mux_dfc:auto_generated.result[3]
result[4] <= mux_dfc:auto_generated.result[4]
result[5] <= mux_dfc:auto_generated.result[5]
result[6] <= mux_dfc:auto_generated.result[6]
result[7] <= mux_dfc:auto_generated.result[7]


|uart|UARTCTRL:inst3|lpm_mux:$00014|mux_dfc:auto_generated
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE


|uart|UARTCTRL:inst3|lpm_dff:$00016
clock => dffs[0].CLK
enable => dffs[0].ENA
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
sconst => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= shiftout~0.DB_MAX_OUTPUT_PORT_TYPE


|uart|UARTCTRL:inst3|lpm_dff:$00018
clock => dffs[0].CLK
enable => dffs[0].ENA
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
sconst => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= shiftout~0.DB_MAX_OUTPUT_PORT_TYPE


|uart|UARTCTRL:inst3|lpm_dff:$00020
clock => dffs[0].CLK
enable => dffs[0].ENA
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
sconst => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= shiftout~0.DB_MAX_OUTPUT_PORT_TYPE


|uart|TX:5
clk => lpm_dff:$00017.clock
clk => lpm_dff:$00015.clock
clk => clk_pdiv:$00001.clk
clk => Txss~0.IN1
reset => shiftreg:$00007.clear
reset => Txss~2.IN1
TxReg[0] => TxSRd[0].IN1
TxReg[1] => TxSRd[1].IN1
TxReg[2] => TxSRd[2].IN1
TxReg[3] => TxSRd[3].IN1
TxReg[4] => TxSRd[4].IN1
TxReg[5] => TxSRd[5].IN1
TxReg[6] => TxSRd[6].IN1
TxReg[7] => TxSRd[7].IN1
DIVISOR[0] => clk_pdiv:$00001.d[0]
DIVISOR[1] => clk_pdiv:$00001.d[1]
DIVISOR[2] => clk_pdiv:$00001.d[2]
DIVISOR[3] => clk_pdiv:$00001.d[3]
DIVISOR[4] => clk_pdiv:$00001.d[4]
DIVISOR[5] => clk_pdiv:$00001.d[5]
DIVISOR[6] => clk_pdiv:$00001.d[6]
DIVISOR[7] => clk_pdiv:$00001.d[7]
DIVISOR[8] => clk_pdiv:$00001.d[8]
DIVISOR[9] => clk_pdiv:$00001.d[9]
DIVISOR[10] => clk_pdiv:$00001.d[10]
DIVISOR[11] => clk_pdiv:$00001.d[11]
DIVISOR[12] => clk_pdiv:$00001.d[12]
DIVISOR[13] => clk_pdiv:$00001.d[13]
DIVISOR[14] => clk_pdiv:$00001.d[14]
DIVISOR[15] => clk_pdiv:$00001.d[15]
DIVISOR[16] => clk_pdiv:$00001.d[16]
TxSTART => lpm_dff:$00015.aset
TxEND <= TxEND~0.DB_MAX_OUTPUT_PORT_TYPE
TxSTATUS <= lpm_dff:$00017.q[0]
TX <= lpm_dff:$00005.q[0]
XOUT[0] <= XOUT[0]~3.DB_MAX_OUTPUT_PORT_TYPE
XOUT[1] <= XOUT[1]~2.DB_MAX_OUTPUT_PORT_TYPE
XOUT[2] <= XOUT[2]~1.DB_MAX_OUTPUT_PORT_TYPE
XOUT[3] <= XOUT[3]~0.DB_MAX_OUTPUT_PORT_TYPE


|uart|TX:5|clk_pdiv:$00001
CLK => lpm_dff:$00004.clock
CLK => lpm_counter:$00002.clock
D[0] => lpm_compare:$00000.datab[0]
D[1] => lpm_compare:$00000.datab[1]
D[2] => lpm_compare:$00000.datab[2]
D[3] => lpm_compare:$00000.datab[3]
D[4] => lpm_compare:$00000.datab[4]
D[5] => lpm_compare:$00000.datab[5]
D[6] => lpm_compare:$00000.datab[6]
D[7] => lpm_compare:$00000.datab[7]
D[8] => lpm_compare:$00000.datab[8]
D[9] => lpm_compare:$00000.datab[9]
D[10] => lpm_compare:$00000.datab[10]
D[11] => lpm_compare:$00000.datab[11]
D[12] => lpm_compare:$00000.datab[12]
D[13] => lpm_compare:$00000.datab[13]
D[14] => lpm_compare:$00000.datab[14]
D[15] => lpm_compare:$00000.datab[15]
D[16] => lpm_compare:$00000.datab[16]
enable => lpm_dff:$00004.enable
enable => lpm_counter:$00002.clk_en
RESET => lpm_counter:$00002.aclr
OUT <= lpm_dff:$00004.q[0]
q[0] <= lpm_counter:$00002.q[0]
q[1] <= lpm_counter:$00002.q[1]
q[2] <= lpm_counter:$00002.q[2]
q[3] <= lpm_counter:$00002.q[3]
q[4] <= lpm_counter:$00002.q[4]
q[5] <= lpm_counter:$00002.q[5]
q[6] <= lpm_counter:$00002.q[6]
q[7] <= lpm_counter:$00002.q[7]
q[8] <= lpm_counter:$00002.q[8]
q[9] <= lpm_counter:$00002.q[9]
q[10] <= lpm_counter:$00002.q[10]
q[11] <= lpm_counter:$00002.q[11]
q[12] <= lpm_counter:$00002.q[12]
q[13] <= lpm_counter:$00002.q[13]
q[14] <= lpm_counter:$00002.q[14]
q[15] <= lpm_counter:$00002.q[15]
q[16] <= lpm_counter:$00002.q[16]


|uart|TX:5|clk_pdiv:$00001|lpm_compare:$00000
dataa[0] => cmpr_ied:auto_generated.dataa[0]
dataa[1] => cmpr_ied:auto_generated.dataa[1]
dataa[2] => cmpr_ied:auto_generated.dataa[2]
dataa[3] => cmpr_ied:auto_generated.dataa[3]
dataa[4] => cmpr_ied:auto_generated.dataa[4]
dataa[5] => cmpr_ied:auto_generated.dataa[5]
dataa[6] => cmpr_ied:auto_generated.dataa[6]
dataa[7] => cmpr_ied:auto_generated.dataa[7]
dataa[8] => cmpr_ied:auto_generated.dataa[8]
dataa[9] => cmpr_ied:auto_generated.dataa[9]
dataa[10] => cmpr_ied:auto_generated.dataa[10]
dataa[11] => cmpr_ied:auto_generated.dataa[11]
dataa[12] => cmpr_ied:auto_generated.dataa[12]
dataa[13] => cmpr_ied:auto_generated.dataa[13]
dataa[14] => cmpr_ied:auto_generated.dataa[14]
dataa[15] => cmpr_ied:auto_generated.dataa[15]
dataa[16] => cmpr_ied:auto_generated.dataa[16]
datab[0] => cmpr_ied:auto_generated.datab[0]
datab[1] => cmpr_ied:auto_generated.datab[1]
datab[2] => cmpr_ied:auto_generated.datab[2]
datab[3] => cmpr_ied:auto_generated.datab[3]
datab[4] => cmpr_ied:auto_generated.datab[4]
datab[5] => cmpr_ied:auto_generated.datab[5]
datab[6] => cmpr_ied:auto_generated.datab[6]
datab[7] => cmpr_ied:auto_generated.datab[7]
datab[8] => cmpr_ied:auto_generated.datab[8]
datab[9] => cmpr_ied:auto_generated.datab[9]
datab[10] => cmpr_ied:auto_generated.datab[10]
datab[11] => cmpr_ied:auto_generated.datab[11]
datab[12] => cmpr_ied:auto_generated.datab[12]
datab[13] => cmpr_ied:auto_generated.datab[13]
datab[14] => cmpr_ied:auto_generated.datab[14]
datab[15] => cmpr_ied:auto_generated.datab[15]
datab[16] => cmpr_ied:auto_generated.datab[16]
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
alb <= <GND>
aeb <= cmpr_ied:auto_generated.aeb
agb <= <GND>
aleb <= <GND>
aneb <= <GND>
ageb <= <GND>


|uart|TX:5|clk_pdiv:$00001|lpm_compare:$00000|cmpr_ied:auto_generated
aeb <= aeb_int.DB_MAX_OUTPUT_PORT_TYPE


|uart|TX:5|clk_pdiv:$00001|lpm_counter:$00002
clock => cntr_d8h:auto_generated.clock
clk_en => cntr_d8h:auto_generated.clk_en
cnt_en => ~NO_FANOUT~
updown => ~NO_FANOUT~