uart.qsf

FPGA-UART异步通信串行口设计实例

# Copyright (C) 1991-2005 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		uart_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:05:09  JUNE 16, 2004"
set_global_assignment -name LAST_QUARTUS_VERSION 7.1
set_global_assignment -name AHDL_FILE clk_pdiv.tdf
set_global_assignment -name AHDL_FILE filt_tpl.tdf
set_global_assignment -name AHDL_FILE filterx.tdf
set_global_assignment -name AHDL_FILE Par_Gen.tdf
set_global_assignment -name AHDL_FILE rx.tdf
set_global_assignment -name AHDL_FILE shiftreg.tdf
set_global_assignment -name AHDL_FILE tx.tdf
set_global_assignment -name GDF_FILE uart.gdf
set_global_assignment -name AHDL_FILE uartctrl.tdf
set_global_assignment -name VECTOR_WAVEFORM_FILE uart.vwf

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL SYNPLIFY
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name TOP_LEVEL_ENTITY uart

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C20F400C8

# Simulator Assignments
# =====================
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name GLITCH_INTERVAL "1 ns"

# ---------------------------------------------
# start EDA_TOOL_SETTINGS(eda_design_synthesis)

	# Analysis & Synthesis Assignments
	# ================================
	set_global_assignment -name EDA_LMF_FILE synplcty.lmf -section_id eda_design_synthesis
	set_global_assignment -name EDA_INPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_design_synthesis

# end EDA_TOOL_SETTINGS(eda_design_synthesis)
# -------------------------------------------