rx.bsf

FPGA-UART异步通信串行口设计实例

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
*/
(header "symbol" (version "1.1"))
(symbol
	(rect 64 64 264 312)
	(text "Rx" (rect 5 0 19 12)(font "Arial" ))
	(text "inst" (rect 16 221 33 233)(font "Arial" ))
	(port
		(pt 0 152)
		(input)
		(text "clk" (rect 0 0 14 12)(font "Arial" ))
		(text "clk" (rect 29 144 43 156)(font "Arial" ))
		(line (pt 0 152)(pt 16 152)(line_width 1))
	)
	(port
		(pt 0 136)
		(input)
		(text "reset" (rect 0 0 24 12)(font "Arial" ))
		(text "reset" (rect 29 128 53 140)(font "Arial" ))
		(line (pt 0 136)(pt 16 136)(line_width 1))
	)
	(port
		(pt 0 56)
		(input)
		(text "CfgReg[6..0]" (rect 0 0 64 12)(font "Arial" ))
		(text "CfgReg[6..0]" (rect 29 48 93 60)(font "Arial" ))
		(line (pt 0 56)(pt 16 56)(line_width 3))
	)
	(port
		(pt 0 40)
		(input)
		(text "DIVISOR[16..0]" (rect 0 0 77 12)(font "Arial" ))
		(text "DIVISOR[16..0]" (rect 29 32 106 44)(font "Arial" ))
		(line (pt 0 40)(pt 16 40)(line_width 3))
	)
	(port
		(pt 0 104)
		(input)
		(text "RxSTART" (rect 0 0 48 12)(font "Arial" ))
		(text "RxSTART" (rect 29 96 77 108)(font "Arial" ))
		(line (pt 0 104)(pt 16 104)(line_width 1))
	)
	(port
		(pt 200 40)
		(input)
		(text "Rx" (rect 0 0 14 12)(font "Arial" ))
		(text "Rx" (rect 162 32 176 44)(font "Arial" ))
		(line (pt 184 40)(pt 200 40)(line_width 1))
	)
	(port
		(pt 0 120)
		(output)
		(text "RxEND" (rect 0 0 37 12)(font "Arial" ))
		(text "RxEND" (rect 24 112 61 124)(font "Arial" ))
		(line (pt 16 120)(pt 0 120)(line_width 1))
	)
	(port
		(pt 0 88)
		(output)
		(text "RxReg[7..0]" (rect 0 0 60 12)(font "Arial" ))
		(text "RxReg[7..0]" (rect 24 80 84 92)(font "Arial" ))
		(line (pt 16 88)(pt 0 88)(line_width 3))
	)
	(port
		(pt 0 72)
		(output)
		(text "RxStatus[4..0]" (rect 0 0 71 12)(font "Arial" ))
		(text "RxStatus[4..0]" (rect 24 64 95 76)(font "Arial" ))
		(line (pt 16 72)(pt 0 72)(line_width 3))
	)
	(parameter
		"FILTER_DEPTH"
		""
		""
	)
	(drawing
		(rectangle (rect 16 16 184 232)(line_width 1))
	)
	(annotation_block (parameter)(rect 216 -16 328 16))
)