autoled.ucf

一套基于XILIX,SPATAN2,XC2S200 芯片实验板上的,10个典型VRILOGHDL的FPGA实验

net rst LOC = P57;
net displayclk LOC = P80;#100khz

net display<0> loc = P33;
net display<1> loc = P30;
net display<2> loc = P27;
net display<3> loc = P23;
net display<4> loc = P21;
net display<5> loc = P18;
net display<6> loc = P16;
net display<7> loc = P14;

net scan<0> LOC = P3;
net scan<1> LOC = P5;
net scan<2> LOC = P7;
net scan<3> LOC = P9;