led_s.v

一套基于XILIX,SPATAN2,XC2S200 芯片实验板上的,10个典型VRILOGHDL的FPGA实验

module LED_S(rst, clk_in, synclk, data);
    input rst, clk_in;
    output synclk;
    output data;
	reg synclk, data;

	reg [3:0] i,j;
	reg [7:0] count;
	reg [3:0] num[5:0];
	reg [7:0] temp;

	parameter ZERO = 8'b11111100, ONE = 8'b01100000, TWO = 8'b11011010;
	parameter THREE = 8'b11110010, FOUR =8'b01100110;
	parameter FIVE = 8'b10110110, SIX = 8'b10111110, SEVEN =8'b11100000;
	parameter EIGHT = 8'b11111110, NINE = 8'b11110110, BLANK = 8'b00000000;

    always @(posedge clk_in or negedge rst)
    begin
		if (!rst)
		begin
			count = 0;
			synclk = 1;

			num[0] = 0;
			num[1] = 1;
			num[2] = 2;
			num[3] = 3;
			num[4] = 4;
			num[5] = 5;
		end
		else
		begin
			if (count < 96)
			begin
				synclk = ~synclk;
				count = count + 1;
			end
			else
			begin
				synclk = synclk;
				count = count;
			end			
		end	    		
	end

	always @(negedge synclk or negedge rst)
	begin
		if (!rst)
		begin
			i = 0;
			j = 0;
		end
		else
		begin			
			case (num[i])
			0 : temp = ZERO;
			1 :	temp = ONE;
			2 :	temp = TWO;
			3 :	temp = THREE;
			4 :	temp = FOUR;
			5 :	temp = FIVE;
			6 :	temp = SIX;
			7 :	temp = SEVEN;
			8 :	temp = EIGHT;
			9 :	temp = NINE;
			//default temp = BLANK;
			endcase
	
			case (j)
			0 : data = temp[0]; 
			1 :	data = temp[1];
			2 :	data = temp[2];
			3 :	data = temp[3];
			4 :	data = temp[4];
			5 :	data = temp[5];
			6 :	data = temp[6];
			7 :	data = temp[7];
			//default data = 0;
			endcase
	
			if (j == 7)
			begin
				i = i + 1;
				j = 0;
			end
			else
				j = j + 1;
		end
	end
endmodule