datacollect.ucf

一套基于XILIX,SPATAN2,XC2S200 芯片实验板上的,10个典型VRILOGHDL的FPGA实验

net sysclk loc = p80;
net rst loc = p57;

net adda loc = p14;
net addb loc = p16;
net addc loc = p18;

net oe loc = p23;
net start loc = p27;

net datain<7> loc = p30;
net datain<6> loc = p33;
net datain<5> loc = p35;
net datain<4> loc = p37;
net datain<3> loc = p42;
net datain<2> loc = p44;
net datain<1> loc = p46;
net datain<0> loc = p48;

net led_sel<3> loc = p3;
net led_sel<2> loc = p5;
net led_sel<1> loc = p7;
net led_sel<0> loc = p9;

net led_seg<7> loc = p206;
net led_seg<6> loc = p204;
net led_seg<5> loc = p202;
net led_seg<4> loc = p200;
net led_seg<3> loc = p195;
net led_seg<2> loc = p193;
net led_seg<1> loc = p191;
net led_seg<0> loc = p187;