sig_gen.ucf

一套基于XILIX,SPATAN2,XC2S200 芯片实验板上的,10个典型VRILOGHDL的FPGA实验

net sysclk loc = p80; //1k时最好
net rst_n loc = p57;
net CS loc = p46;
net WR loc = p48;

net mode<1> loc = p102;
net mode<0> loc = p100;

net data<7> loc = p14;
net data<6> loc = p16;
net data<5> loc = p18;
net data<4> loc = p21;
net data<3> loc = p23;
net data<2> loc = p27;
net data<1> loc = p30;
net data<0> loc = p33;