mcu_sram_test.smp_dump.txt

verilog编写基于FPGA的示波器核心实现

State Machine - |mcu_sram_test|osc:inst2|osc_control:inst|state
Name state.WAIT2 state.WAIT1 state.ALLIN state.IDLE 
state.IDLE 0 0 0 0 
state.WAIT1 0 1 0 1 
state.ALLIN 0 0 1 1 
state.WAIT2 1 0 0 1 

State Machine - |mcu_sram_test|osc:inst2|osc_display:inst3|state
Name state.NEWCOUNT state.COMPARE5 state.COMPARE4 state.COMPARE3 state.COMPARE2 state.COMPARE1 state.GET 
state.GET 0 0 0 0 0 0 0 
state.COMPARE4 0 0 1 0 0 0 1 
state.COMPARE3 0 0 0 1 0 0 1 
state.NEWCOUNT 1 0 0 0 0 0 1 
state.COMPARE2 0 0 0 0 1 0 1 
state.COMPARE1 0 0 0 0 0 1 1 
state.COMPARE5 0 1 0 0 0 0 1 

State Machine - |mcu_sram_test|sram_control:inst4|state
Name state.RD_ADDRNEW state.RD_DATANEW state.WR_ADDRNEW state.WR_DATANEW state.READY state.IDLE 
state.IDLE 0 0 0 0 0 0 
state.WR_ADDRNEW 0 0 1 0 0 1 
state.RD_ADDRNEW 1 0 0 0 0 1 
state.WR_DATANEW 0 0 0 1 0 1 
state.READY 0 0 0 0 1 1 
state.RD_DATANEW 0 1 0 0 0 1 

State Machine - |mcu_sram_test|mcu_fpga_control:inst8|rd_state
Name rd_state.RD_LOW_T rd_state.RD_LOW rd_state.RD_HIGH_T rd_state.RD_HIGH 
rd_state.RD_HIGH 0 0 0 0 
rd_state.RD_LOW 0 1 0 1 
rd_state.RD_HIGH_T 0 0 1 1 
rd_state.RD_LOW_T 1 0 0 1 

State Machine - |mcu_sram_test|mcu_fpga_control:inst8|wr_state
Name wr_state.WR_VOID wr_state.WR_CMD wr_state.WR_DATA2 wr_state.WR_DATA1 
wr_state.WR_DATA1 0 0 0 0 
wr_state.WR_CMD 0 1 0 1 
wr_state.WR_DATA2 0 0 1 1 
wr_state.WR_VOID 1 0 0 1 

State Machine - |mcu_sram_test|mcu_fpga_control:inst8|wr_ca_state
Name wr_ca_state.100 wr_ca_state.010 wr_ca_state.001 
wr_ca_state.100 0 0 0 
wr_ca_state.001 1 0 1 
wr_ca_state.010 1 1 0 

State Machine - |mcu_sram_test|mcu_fpga_control:inst8|wr_dsram_state
Name wr_dsram_state.100 wr_dsram_state.010 wr_dsram_state.001 
wr_dsram_state.100 0 0 0 
wr_dsram_state.001 1 0 1 
wr_dsram_state.010 1 1 0 

State Machine - |mcu_sram_test|mcu_fpga_control:inst8|wr_ad_state
Name wr_ad_state.100 wr_ad_state.010 wr_ad_state.001 
wr_ad_state.100 0 0 0 
wr_ad_state.001 1 0 1 
wr_ad_state.010 1 1 0 

State Machine - |mcu_sram_test|mcu_fpga_control:inst8|rd_ca_state
Name rd_ca_state.100 rd_ca_state.010 rd_ca_state.001 
rd_ca_state.100 0 0 0 
rd_ca_state.001 1 0 1 
rd_ca_state.010 1 1 0 

State Machine - |mcu_sram_test|mcu_fpga_control:inst8|rd_dsram_state
Name rd_dsram_state.100 rd_dsram_state.010 rd_dsram_state.001 
rd_dsram_state.100 0 0 0 
rd_dsram_state.001 1 0 1 
rd_dsram_state.010 1 1 0 

State Machine - |mcu_sram_test|mcu_fpga_control:inst8|dds_phase_state
Name dds_phase_state.100 dds_phase_state.010 dds_phase_state.001 
dds_phase_state.100 0 0 0 
dds_phase_state.001 1 0 1 
dds_phase_state.010 1 1 0 

State Machine - |mcu_sram_test|mcu_fpga_control:inst8|dds_freq_state
Name dds_freq_state.100 dds_freq_state.010 dds_freq_state.001 
dds_freq_state.100 0 0 0 
dds_freq_state.001 1 0 1 
dds_freq_state.010 1 1 0 

State Machine - |mcu_sram_test|mcu_fpga_control:inst8|osc_mod_state
Name osc_mod_state.100 osc_mod_state.010 osc_mod_state.001 
osc_mod_state.100 0 0 0 
osc_mod_state.001 1 0 1 
osc_mod_state.010 1 1 0