mcu_sram_test.hif

verilog编写基于FPGA的示波器核心实现

CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
E:/mcu_fpga_control.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_t5p1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b
-1
3
data_a
-1
3
clock1
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
wren_b
-1
1
addressstall_b
-1
1
addressstall_a
-1
1
aclr1
-1
1
aclr0
-1
1
data_b
-1
2
clocken1
-1
2
clocken0
-1
2
byteena_b
-1
2
byteena_a
-1
2
}
# include_file {
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
..|..|..|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|..|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|..|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|..|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|..|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|..|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# end
# entity
altsyncram_t5p1
# storage
db|mcu_sram_test.(31).cnf
db|mcu_sram_test.(31).cnf
# case_insensitive
# source_file
db|altsyncram_t5p1.tdf
6f0323197035758002a3eed8cd84a
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
E:|mcu_fpga_control.mif
b4617e91a5da8687b5544af634466da
}
# end
# entity
altsyncram
# storage
db|mcu_sram_test.(32).cnf
db|mcu_sram_test.(32).cnf
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
10
PARAMETER_DEC
USR
NUMWORDS_A
1024
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
8
PARAMETER_DEC
USR
WIDTHAD_B
10
PARAMETER_DEC
USR
NUMWORDS_B
1024
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
sun.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_3ln1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b
-1
3
data_a
-1
3
clock1
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
wren_b
-1
1
addressstall_b
-1
1
addressstall_a
-1
1
aclr1
-1
1
aclr0
-1
1
data_b
-1
2
clocken1
-1
2
clocken0
-1
2
byteena_b
-1
2
byteena_a
-1
2
}
# include_file {
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
..|..|..|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|..|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|..|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|..|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|..|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|..|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# end
# entity
altsyncram_3ln1
# storage
db|mcu_sram_test.(33).cnf
db|mcu_sram_test.(33).cnf
# case_insensitive
# source_file
db|altsyncram_3ln1.tdf
c8dee129d1b4af4ec83c6666239fa
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
sun.mif
192c9a101a826ddffa65efc1be983d
}
# end
# entity
mfreq
# storage
db|mcu_sram_test.(26).cnf
db|mcu_sram_test.(26).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
mfreq.v
db463b76a75f7833284977f5952ff33a
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
N
8
PARAMETER_UNKNOWN
USR
}
# hierarchies {
mfreq:freq8
}
# end
# entity
osc_display
# storage
db|mcu_sram_test.(9).cnf
db|mcu_sram_test.(9).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
osc_display.v
c88769a2a62eba84615f48c5266e
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
GET
0000000001
PARAMETER_BIN
USR
COMPARE1
0000000010
PARAMETER_BIN
USR
COMPARE2
0000000100
PARAMETER_BIN
USR
COMPARE3
0000001000
PARAMETER_BIN
USR
COMPARE4
0000010000
PARAMETER_BIN
USR
COMPARE5
0000100000
PARAMETER_BIN
USR
COMPARE6
0001000000
PARAMETER_BIN
USR
COMPARE7
0010000000
PARAMETER_BIN
USR
COMPARE8
0100000000
PARAMETER_BIN
USR
NEWCOUNT
1000000000
PARAMETER_BIN
USR
}
# hierarchies {
osc:inst2|osc_display:inst3
}
# end
# entity
mcu_sram_test
# storage
db|mcu_sram_test.(0).cnf
db|mcu_sram_test.(0).cnf
# case_insensitive
# source_file
mcu_sram_test.bdf
f156eda54677cb98a5eaf4ee9675f83
24
# hierarchies {
|
}
# end
# entity
mcu_fpga_control
# storage
db|mcu_sram_test.(2).cnf
db|mcu_sram_test.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
mcu_fpga_control.v
74a9e56f1a8137efe991e0f2b7a415a7
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
S1
0001
PARAMETER_BIN
USR
S2
0010
PARAMETER_BIN
USR
S3
0100
PARAMETER_BIN
USR
S4
1000
PARAMETER_BIN
USR
MCUWR
0
PARAMETER_BIN
USR
ADWR
1
PARAMETER_BIN
USR
YES
1
PARAMETER_BIN
USR
NO
0
PARAMETER_BIN
USR
WR_DATA1
0001
PARAMETER_BIN
USR
WR_DATA2
0010
PARAMETER_BIN
USR
WR_CMD
0100
PARAMETER_BIN
USR
WR_VOID
1000
PARAMETER_BIN
USR
RD_HIGH
0001
PARAMETER_BIN
USR
RD_HIGH_T
0010
PARAMETER_BIN
USR
RD_LOW
0100
PARAMETER_BIN
USR
RD_LOW_T
1000
PARAMETER_BIN
USR
WR_ISADDR16
0
PARAMETER_UNKNOWN
USR
WR_ISADDR17
1
PARAMETER_UNKNOWN
USR
WR_ISCOUNT16
2
PARAMETER_UNKNOWN
USR
WR_ISCOUNT17
3
PARAMETER_UNKNOWN
USR
RD_ISADDR16
4
PARAMETER_UNKNOWN
USR
RD_ISADDR17
5
PARAMETER_UNKNOWN
USR
RD_ISCOUNT16
6
PARAMETER_UNKNOWN
USR
RD_ISCOUNT17
7
PARAMETER_UNKNOWN
USR
MCU2SRAM
8
PARAMETER_UNKNOWN
USR
AD2SRAM
9
PARAMETER_UNKNOWN
USR
DDSPHASE
10
PARAMETER_UNKNOWN
USR
DDSFREQ
11
PARAMETER_UNKNOWN
USR
OSC_MOD_ADDR
12
PARAMETER_UNKNOWN
USR
OSC_MOD_DATA
13
PARAMETER_UNKNOWN
USR
}
# hierarchies {
mcu_fpga_control:inst8
}
# end
# entity
sram_control
# storage
db|mcu_sram_test.(7).cnf
db|mcu_sram_test.(7).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sram_control.v
3eae17f8b6a8d37e78dd2c65bc5012ea
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
IDLE
0000001
PARAMETER_BIN
USR
READY
0000010
PARAMETER_BIN
USR
WR_DATANEW
0000100
PARAMETER_BIN
USR
WR_ADDRNEW
0001000
PARAMETER_BIN
USR
RD_DATANEW
0010000
PARAMETER_BIN
USR
RD_ADDRNEW
0100000
PARAMETER_BIN
USR
YES
1
PARAMETER_BIN
USR
NO
0
PARAMETER_BIN
USR
}
# hierarchies {
sram_control:inst4
}
# end
# entity
osc_control
# storage
db|mcu_sram_test.(13).cnf
db|mcu_sram_test.(13).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
osc_control.v
629c624cf0b23aedb1a961c529c11f3e
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
IDLE
0001
PARAMETER_BIN
USR
ALLIN
0010
PARAMETER_BIN
USR
WAIT1
0100
PARAMETER_BIN
USR
WAIT2
1000
PARAMETER_BIN
USR
}
# hierarchies {
osc:inst2|osc_control:inst
}
# end
# entity
osc
# storage
db|mcu_sram_test.(10).cnf
db|mcu_sram_test.(10).cnf
# case_insensitive
# source_file
osc.bdf
8ccfceefba5f6c24e93474e856da29
24
# hierarchies {
osc:inst2
}
# end
# entity
osc_ram
# storage
db|mcu_sram_test.(15).cnf
db|mcu_sram_test.(15).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
osc_ram.v
aa671818e7c66f1a20d19d12eae3c363
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
osc:inst2|osc_ram:inst2
}
# end
# complete