mcu_sram_test.hif

verilog编写基于FPGA的示波器核心实现

-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# end
# entity
altsyncram_1nl2
# storage
db|mcu_sram_test.(28).cnf
db|mcu_sram_test.(28).cnf
# case_insensitive
# source_file
db|altsyncram_1nl2.tdf
f2d2d2902776b6928dbbd3e7bdf5ccf
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_b
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b3
-1
3
data_b2
-1
3
data_b11
-1
3
data_b10
-1
3
data_b1
-1
3
data_b0
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b11
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
dds|sin.mif
1a856388b78d1b28ae12dbdaaedc6fd4
}
# end
# entity
lpm_add_sub0
# storage
db|mcu_sram_test.(29).cnf
db|mcu_sram_test.(29).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
dds|lpm_add_sub0.v
afd0d46cd9212ebf0eb1a97deeaea
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
add
# storage
db|mcu_sram_test.(36).cnf
db|mcu_sram_test.(36).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
dds|add.v
edf473478a9de394140efc95885cf6d
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
decode_ogi
# storage
db|mcu_sram_test.(53).cnf
db|mcu_sram_test.(53).cnf
# case_insensitive
# source_file
db|decode_ogi.tdf
ffc7173ea4e253ca8971cc1a77d92062
6
# used_port {
eq7
-1
3
eq6
-1
3
eq5
-1
3
eq4
-1
3
eq3
-1
3
eq2
-1
3
eq1
-1
3
eq0
-1
3
enable
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
clken
-1
3
aclr
-1
3
}
# end
# entity
altsyncram_sq51
# storage
db|mcu_sram_test.(59).cnf
db|mcu_sram_test.(59).cnf
# case_insensitive
# source_file
db|altsyncram_sq51.tdf
f7546335560c673a72a99f26031ef55
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
dds|cos.mif
d60b31b8e6eb39847a3bc929739f3ee
}
# end
# entity
altsyncram_1r51
# storage
db|mcu_sram_test.(62).cnf
db|mcu_sram_test.(62).cnf
# case_insensitive
# source_file
db|altsyncram_1r51.tdf
95f75ce5c03c4797b1f4ad601e97d5
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
dds|sin.mif
1a856388b78d1b28ae12dbdaaedc6fd4
}
# end
# entity
dds
# storage
db|mcu_sram_test.(1).cnf
db|mcu_sram_test.(1).cnf
# case_insensitive
# source_file
dds.bdf
e2d4f8c7cca51b4a3522887521f2c6a5
24
# end
# entity
dds_control
# storage
db|mcu_sram_test.(63).cnf
db|mcu_sram_test.(63).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
dds_control.v
1f35d7f5b8352952b35ae9083891459
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
IDLE
0000001
PARAMETER_BIN
USR
PHASEIN
0000010
PARAMETER_BIN
USR
WAIT1
0000100
PARAMETER_BIN
USR
FREQL
0001000
PARAMETER_BIN
USR
WAIT2
0010000
PARAMETER_BIN
USR
FREQH
0100000
PARAMETER_BIN
USR
DDS
1000000
PARAMETER_BIN
USR
}
# end
# entity
dds_control
# storage
db|mcu_sram_test.(64).cnf
db|mcu_sram_test.(64).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
dds_control.v
1f35d7f5b8352952b35ae9083891459
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
IDLE
0000001
PARAMETER_BIN
DEF
PHASEIN
0000010
PARAMETER_BIN
DEF
WAIT1
0000100
PARAMETER_BIN
DEF
FREQL
0001000
PARAMETER_BIN
DEF
WAIT2
0010000
PARAMETER_BIN
DEF
FREQH
0100000
PARAMETER_BIN
DEF
DDS
1000000
PARAMETER_BIN
DEF
}
# end
# entity
dds_lut
# storage
db|mcu_sram_test.(8).cnf
db|mcu_sram_test.(8).cnf
# case_insensitive
# source_file
dds|dds_lut.bdf
6c4322462bebcbf6786cfa623b99bda
24
# end
# entity
altsyncram_fsl1
# storage
db|mcu_sram_test.(68).cnf
db|mcu_sram_test.(68).cnf
# case_insensitive
# source_file
db|altsyncram_fsl1.tdf
a47649541096cc96c975a82adc06158
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
none
0
}
# end
# entity
altsyncram_usp1
# storage
db|mcu_sram_test.(70).cnf
db|mcu_sram_test.(70).cnf
# case_insensitive
# source_file
db|altsyncram_usp1.tdf
a6c021678fdc1d7325a773976672f893
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
rden_b
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
none
0
}
# hierarchies {
osc:inst2|osc_ram:inst2|altsyncram:altsyncram_component|altsyncram_usp1:auto_generated
}
# end
# entity
lpm_mux
# storage
db|mcu_sram_test.(6).cnf
db|mcu_sram_test.(6).cnf
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|lpm_mux.tdf
9bf66e437b499c0f0b81c977a5a50
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
16
PARAMETER_DEC
USR
LPM_SIZE
2
PARAMETER_DEC
USR
LPM_WIDTHS
1
PARAMETER_DEC
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
mux_pgc
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
}
# used_port {
sel
-1
3
result
-1
3
data
-1
3
}
# include_file {
..|..|..|altera|quartus60|libraries|megafunctions|muxlut.inc
f172666ca13e5e31e17e3f6cb35af52
..|..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|altera|quartus60|libraries|megafunctions|bypassff.inc
8e8df160d449a63ec15dc86ecf2b373f
..|..|..|altera|quartus60|libraries|megafunctions|altshift.inc
70fa13aee7d6d160ef20b2de32813a
}
# hierarchies {
mux_sram:inst|lpm_mux:lpm_mux_component
}
# end
# entity
altsyncram
# storage
db|mcu_sram_test.(12).cnf
db|mcu_sram_test.(12).cnf
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8