mcu_sram_test.fnsim.qmsg

verilog编写基于FPGA的示波器核心实现

{ "Info" "ISGN_MEGAFN_DESCENDANT" "dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[1\]\|a_csnbuffer:oflow_node dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[1\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "addcore.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/addcore.tdf" 94 2 0 } } { "dds/add.v" "" { Text "F:/fpga test/mcu_sram beta1.1/dds/add.v" 66 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component " "Info: Instantiated megafunction \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Info: Parameter \"lpm_direction\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO " "Info: Parameter \"lpm_hint\" = \"ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Info: Parameter \"lpm_pipeline\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ADD_SUB " "Info: Parameter \"lpm_type\" = \"LPM_ADD_SUB\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 32 " "Info: Parameter \"lpm_width\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "dds/add.v" "" { Text "F:/fpga test/mcu_sram beta1.1/dds/add.v" 66 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_csnbuffer dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[1\]\|a_csnbuffer:result_node " "Info: Elaborating entity \"a_csnbuffer\" for hierarchy \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[1\]\|a_csnbuffer:result_node\"" {  } { { "addcore.tdf" "result_node" { Text "f:/altera/quartus60/libraries/megafunctions/addcore.tdf" 120 6 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[1\]\|a_csnbuffer:result_node dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[1\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "addcore.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/addcore.tdf" 120 6 0 } } { "dds/add.v" "" { Text "F:/fpga test/mcu_sram beta1.1/dds/add.v" 66 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component " "Info: Instantiated megafunction \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Info: Parameter \"lpm_direction\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO " "Info: Parameter \"lpm_hint\" = \"ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Info: Parameter \"lpm_pipeline\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ADD_SUB " "Info: Parameter \"lpm_type\" = \"LPM_ADD_SUB\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 32 " "Info: Parameter \"lpm_width\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "dds/add.v" "" { Text "F:/fpga test/mcu_sram beta1.1/dds/add.v" 66 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addcore dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\] " "Info: Elaborating entity \"addcore\" for hierarchy \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\"" {  } { { "lpm_add_sub.tdf" "adder1\[0\]" { Text "f:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 240 11 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\] dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\", which is child of megafunction instantiation \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "lpm_add_sub.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 240 11 0 } } { "dds/add.v" "" { Text "F:/fpga test/mcu_sram beta1.1/dds/add.v" 66 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component " "Info: Instantiated megafunction \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Info: Parameter \"lpm_direction\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO " "Info: Parameter \"lpm_hint\" = \"ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Info: Parameter \"lpm_pipeline\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ADD_SUB " "Info: Parameter \"lpm_type\" = \"LPM_ADD_SUB\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 32 " "Info: Parameter \"lpm_width\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "dds/add.v" "" { Text "F:/fpga test/mcu_sram beta1.1/dds/add.v" 66 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_csnbuffer dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node " "Info: Elaborating entity \"a_csnbuffer\" for hierarchy \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\"" {  } { { "addcore.tdf" "result_node" { Text "f:/altera/quartus60/libraries/megafunctions/addcore.tdf" 120 6 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "addcore.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/addcore.tdf" 120 6 0 } } { "dds/add.v" "" { Text "F:/fpga test/mcu_sram beta1.1/dds/add.v" 66 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component " "Info: Instantiated megafunction \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Info: Parameter \"lpm_direction\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO " "Info: Parameter \"lpm_hint\" = \"ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Info: Parameter \"lpm_pipeline\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ADD_SUB " "Info: Parameter \"lpm_type\" = \"LPM_ADD_SUB\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 32 " "Info: Parameter \"lpm_width\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "dds/add.v" "" { Text "F:/fpga test/mcu_sram beta1.1/dds/add.v" 66 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_csnbuffer dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:cout_node " "Info: Elaborating entity \"a_csnbuffer\" for hierarchy \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:cout_node\"" {  } { { "addcore.tdf" "cout_node" { Text "f:/altera/quartus60/libraries/megafunctions/addcore.tdf" 122 6 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:cout_node dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:cout_node\", which is child of megafunction instantiation \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "addcore.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/addcore.tdf" 122 6 0 } } { "dds/add.v" "" { Text "F:/fpga test/mcu_sram beta1.1/dds/add.v" 66 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component " "Info: Instantiated megafunction \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Info: Parameter \"lpm_direction\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO " "Info: Parameter \"lpm_hint\" = \"ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Info: Parameter \"lpm_pipeline\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ADD_SUB " "Info: Parameter \"lpm_type\" = \"LPM_ADD_SUB\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 32 " "Info: Parameter \"lpm_width\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "dds/add.v" "" { Text "F:/fpga test/mcu_sram beta1.1/dds/add.v" 66 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addcore dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\] " "Info: Elaborating entity \"addcore\" for hierarchy \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\"" {  } { { "lpm_add_sub.tdf" "adder1_0\[1\]" { Text "f:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 245 14 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\] dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\", which is child of megafunction instantiation \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "lpm_add_sub.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 245 14 0 } } { "dds/add.v" "" { Text "F:/fpga test/mcu_sram beta1.1/dds/add.v" 66 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component " "Info: Instantiated megafunction \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Info: Parameter \"lpm_direction\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO " "Info: Parameter \"lpm_hint\" = \"ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Info: Parameter \"lpm_pipeline\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ADD_SUB " "Info: Parameter \"lpm_type\" = \"LPM_ADD_SUB\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 32 " "Info: Parameter \"lpm_width\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "dds/add.v" "" { Text "F:/fpga test/mcu_sram beta1.1/dds/add.v" 66 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../altera/quartus60/libraries/megafunctions/bypassff.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/bypassff.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 bypassff " "Info: Found entity 1: bypassff" {  } { { "bypassff.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/bypassff.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bypassff dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|bypassff:datab1_ff\[1\]\[1\] " "Info: Elaborating entity \"bypassff\" for hierarchy \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|bypassff:datab1_ff\[1\]\[1\]\"" {  } { { "lpm_add_sub.tdf" "datab1_ff\[1\]\[1\]" { Text "f:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 251 13 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|bypassff:datab1_ff\[1\]\[1\] dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|bypassff:datab1_ff\[1\]\[1\]\", which is child of megafunction instantiation \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "lpm_add_sub.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 251 13 0 } } { "dds/add.v" "" { Text "F:/fpga test/mcu_sram beta1.1/dds/add.v" 66 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component " "Info: Instantiated megafunction \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Info: Parameter \"lpm_direction\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO " "Info: Parameter \"lpm_hint\" = \"ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Info: Parameter \"lpm_pipeline\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ADD_SUB " "Info: Parameter \"lpm_type\" = \"LPM_ADD_SUB\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 32 " "Info: Parameter \"lpm_width\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "dds/add.v" "" { Text "F:/fpga test/mcu_sram beta1.1/dds/add.v" 66 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bypassff dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|bypassff:datab1_ff\[0\]\[1\] " "Info: Elaborating entity \"bypassff\" for hierarchy \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|bypassff:datab1_ff\[0\]\[1\]\"" {  } { { "lpm_add_sub.tdf" "datab1_ff\[0\]\[1\]" { Text "f:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 251 13 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|bypassff:datab1_ff\[0\]\[1\] dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\|bypassff:datab1_ff\[0\]\[1\]\", which is child of megafunction instantiation \"dds:inst1\|add:inst6\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "lpm_add_sub.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 251 13 0 } } { "dds/add.v" "" { Text "F:/fpga