mcu_sram_test.fnsim.qmsg

verilog编写基于FPGA的示波器核心实现

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram dds:inst1\|dds_lut:inst5\|ram:inst7\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"dds:inst1\|dds_lut:inst5\|ram:inst7\|altsyncram:altsyncram_component\"" {  } { { "dds/ram.tdf" "altsyncram_component" { Text "F:/fpga test/mcu_sram beta1.1/dds/ram.tdf" 50 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "dds:inst1\|dds_lut:inst5\|ram:inst7\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"dds:inst1\|dds_lut:inst5\|ram:inst7\|altsyncram:altsyncram_component\"" {  } { { "dds/ram.tdf" "" { Text "F:/fpga test/mcu_sram beta1.1/dds/ram.tdf" 50 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_vpl1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_vpl1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_vpl1 " "Info: Found entity 1: altsyncram_vpl1" {  } { { "db/altsyncram_vpl1.tdf" "" { Text "F:/fpga test/mcu_sram beta1.1/db/altsyncram_vpl1.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_vpl1 dds:inst1\|dds_lut:inst5\|ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated " "Info: Elaborating entity \"altsyncram_vpl1\" for hierarchy \"dds:inst1\|dds_lut:inst5\|ram:inst7\|altsyncram:altsyncram_component\|altsyncram_vpl1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "f:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "square dds:inst1\|dds_lut:inst5\|square:inst2 " "Info: Elaborating entity \"square\" for hierarchy \"dds:inst1\|dds_lut:inst5\|square:inst2\"" {  } { { "dds/dds_lut.bdf" "inst2" { Schematic "F:/fpga test/mcu_sram beta1.1/dds/dds_lut.bdf" { { 376 688 848 456 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram dds:inst1\|dds_lut:inst5\|square:inst2\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"dds:inst1\|dds_lut:inst5\|square:inst2\|altsyncram:altsyncram_component\"" {  } { { "dds/square.tdf" "altsyncram_component" { Text "F:/fpga test/mcu_sram beta1.1/dds/square.tdf" 45 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "dds:inst1\|dds_lut:inst5\|square:inst2\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"dds:inst1\|dds_lut:inst5\|square:inst2\|altsyncram:altsyncram_component\"" {  } { { "dds/square.tdf" "" { Text "F:/fpga test/mcu_sram beta1.1/dds/square.tdf" 45 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_3261.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_3261.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_3261 " "Info: Found entity 1: altsyncram_3261" {  } { { "db/altsyncram_3261.tdf" "" { Text "F:/fpga test/mcu_sram beta1.1/db/altsyncram_3261.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_3261 dds:inst1\|dds_lut:inst5\|square:inst2\|altsyncram:altsyncram_component\|altsyncram_3261:auto_generated " "Info: Elaborating entity \"altsyncram_3261\" for hierarchy \"dds:inst1\|dds_lut:inst5\|square:inst2\|altsyncram:altsyncram_component\|altsyncram_3261:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "f:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cos_rom dds:inst1\|dds_lut:inst5\|cos_rom:inst1 " "Info: Elaborating entity \"cos_rom\" for hierarchy \"dds:inst1\|dds_lut:inst5\|cos_rom:inst1\"" {  } { { "dds/dds_lut.bdf" "inst1" { Schematic "F:/fpga test/mcu_sram beta1.1/dds/dds_lut.bdf" { { 264 688 848 344 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram dds:inst1\|dds_lut:inst5\|cos_rom:inst1\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"dds:inst1\|dds_lut:inst5\|cos_rom:inst1\|altsyncram:altsyncram_component\"" {  } { { "dds/cos_rom.tdf" "altsyncram_component" { Text "F:/fpga test/mcu_sram beta1.1/dds/cos_rom.tdf" 45 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "dds:inst1\|dds_lut:inst5\|cos_rom:inst1\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"dds:inst1\|dds_lut:inst5\|cos_rom:inst1\|altsyncram:altsyncram_component\"" {  } { { "dds/cos_rom.tdf" "" { Text "F:/fpga test/mcu_sram beta1.1/dds/cos_rom.tdf" 45 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_sq51.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_sq51.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_sq51 " "Info: Found entity 1: altsyncram_sq51" {  } { { "db/altsyncram_sq51.tdf" "" { Text "F:/fpga test/mcu_sram beta1.1/db/altsyncram_sq51.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_sq51 dds:inst1\|dds_lut:inst5\|cos_rom:inst1\|altsyncram:altsyncram_component\|altsyncram_sq51:auto_generated " "Info: Elaborating entity \"altsyncram_sq51\" for hierarchy \"dds:inst1\|dds_lut:inst5\|cos_rom:inst1\|altsyncram:altsyncram_component\|altsyncram_sq51:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "f:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sin_rom dds:inst1\|dds_lut:inst5\|sin_rom:inst " "Info: Elaborating entity \"sin_rom\" for hierarchy \"dds:inst1\|dds_lut:inst5\|sin_rom:inst\"" {  } { { "dds/dds_lut.bdf" "inst" { Schematic "F:/fpga test/mcu_sram beta1.1/dds/dds_lut.bdf" { { 160 688 848 240 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram dds:inst1\|dds_lut:inst5\|sin_rom:inst\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"dds:inst1\|dds_lut:inst5\|sin_rom:inst\|altsyncram:altsyncram_component\"" {  } { { "dds/sin_rom.tdf" "altsyncram_component" { Text "F:/fpga test/mcu_sram beta1.1/dds/sin_rom.tdf" 45 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "dds:inst1\|dds_lut:inst5\|sin_rom:inst\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"dds:inst1\|dds_lut:inst5\|sin_rom:inst\|altsyncram:altsyncram_component\"" {  } { { "dds/sin_rom.tdf" "" { Text "F:/fpga test/mcu_sram beta1.1/dds/sin_rom.tdf" 45 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_1r51.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_1r51.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_1r51 " "Info: Found entity 1: altsyncram_1r51" {  } { { "db/altsyncram_1r51.tdf" "" { Text "F:/fpga test/mcu_sram beta1.1/db/altsyncram_1r51.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_1r51 dds:inst1\|dds_lut:inst5\|sin_rom:inst\|altsyncram:altsyncram_component\|altsyncram_1r51:auto_generated " "Info: Elaborating entity \"altsyncram_1r51\" for hierarchy \"dds:inst1\|dds_lut:inst5\|sin_rom:inst\|altsyncram:altsyncram_component\|altsyncram_1r51:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "f:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub0 dds:inst1\|lpm_add_sub0:inst7 " "Info: Elaborating entity \"lpm_add_sub0\" for hierarchy \"dds:inst1\|lpm_add_sub0:inst7\"" {  } { { "dds.bdf" "inst7" { Schematic "F:/fpga test/mcu_sram beta1.1/dds.bdf" { { 376 528 688 472 "inst7" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub dds:inst1\|lpm_add_sub0:inst7\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"dds:inst1\|lpm_add_sub0:inst7\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "dds/lpm_add_sub0.v" "lpm_add_sub_component" { Text "F:/fpga test/mcu_sram beta1.1/dds/lpm_add_sub0.v" 62 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "dds:inst1\|lpm_add_sub0:inst7\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"dds:inst1\|lpm_add_sub0:inst7\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "dds/lpm_add_sub0.v" "" { Text "F:/fpga test/mcu_sram beta1.1/dds/lpm_add_sub0.v" 62 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../altera/quartus60/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}