mcu_sram_test.fnsim.qmsg

verilog编写基于FPGA的示波器核心实现

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "osc_control.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file osc_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 osc_control " "Info: Found entity 1: osc_control" {  } { { "osc_control.v" "" { Text "F:/fpga test/mcu_sram beta1.1/osc_control.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "osc_display.v(28) " "Warning (10273): Verilog HDL warning at osc_display.v(28): extended using \"x\" or \"z\"" {  } { { "osc_display.v" "" { Text "F:/fpga test/mcu_sram beta1.1/osc_display.v" 28 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "osc_display.v(29) " "Warning (10273): Verilog HDL warning at osc_display.v(29): extended using \"x\" or \"z\"" {  } { { "osc_display.v" "" { Text "F:/fpga test/mcu_sram beta1.1/osc_display.v" 29 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "osc_display.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file osc_display.v" { { "Info" "ISGN_ENTITY_NAME" "1 osc_display " "Info: Found entity 1: osc_display" {  } { { "osc_display.v" "" { Text "F:/fpga test/mcu_sram beta1.1/osc_display.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "mcu_sram_test " "Info: Elaborating entity \"mcu_sram_test\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mcu_fpga_control mcu_fpga_control:inst3 " "Info: Elaborating entity \"mcu_fpga_control\" for hierarchy \"mcu_fpga_control:inst3\"" {  } { { "mcu_sram_test.bdf" "inst3" { Schematic "F:/fpga test/mcu_sram beta1.1/mcu_sram_test.bdf" { { -472 160 368 -216 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "mcu_fpga_control.v(107) " "Info (10264): Verilog HDL Case Statement information at mcu_fpga_control.v(107): all case item expressions in this case statement are onehot" {  } { { "mcu_fpga_control.v" "" { Text "F:/fpga test/mcu_sram beta1.1/mcu_fpga_control.v" 107 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sram_control sram_control:inst4 " "Info: Elaborating entity \"sram_control\" for hierarchy \"sram_control:inst4\"" {  } { { "mcu_sram_test.bdf" "inst4" { Schematic "F:/fpga test/mcu_sram beta1.1/mcu_sram_test.bdf" { { -456 504 720 -232 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "sram_control.v(92) " "Info (10264): Verilog HDL Case Statement information at sram_control.v(92): all case item expressions in this case statement are onehot" {  } { { "sram_control.v" "" { Text "F:/fpga test/mcu_sram beta1.1/sram_control.v" 92 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_sram mux_sram:inst " "Info: Elaborating entity \"mux_sram\" for hierarchy \"mux_sram:inst\"" {  } { { "mcu_sram_test.bdf" "inst" { Schematic "F:/fpga test/mcu_sram beta1.1/mcu_sram_test.bdf" { { -688 464 616 -608 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../altera/quartus60/libraries/megafunctions/lpm_mux.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/lpm_mux.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mux " "Info: Found entity 1: lpm_mux" {  } { { "lpm_mux.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/lpm_mux.tdf" 72 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mux mux_sram:inst\|lpm_mux:lpm_mux_component " "Info: Elaborating entity \"lpm_mux\" for hierarchy \"mux_sram:inst\|lpm_mux:lpm_mux_component\"" {  } { { "mux_sram.v" "lpm_mux_component" { Text "F:/fpga test/mcu_sram beta1.1/mux_sram.v" 65 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "mux_sram:inst\|lpm_mux:lpm_mux_component " "Info: Elaborated megafunction instantiation \"mux_sram:inst\|lpm_mux:lpm_mux_component\"" {  } { { "mux_sram.v" "" { Text "F:/fpga test/mcu_sram beta1.1/mux_sram.v" 65 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_pgc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_pgc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_pgc " "Info: Found entity 1: mux_pgc" {  } { { "db/mux_pgc.tdf" "" { Text "F:/fpga test/mcu_sram beta1.1/db/mux_pgc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_pgc mux_sram:inst\|lpm_mux:lpm_mux_component\|mux_pgc:auto_generated " "Info: Elaborating entity \"mux_pgc\" for hierarchy \"mux_sram:inst\|lpm_mux:lpm_mux_component\|mux_pgc:auto_generated\"" {  } { { "lpm_mux.tdf" "auto_generated" { Text "f:/altera/quartus60/libraries/megafunctions/lpm_mux.tdf" 84 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dds dds:inst1 " "Info: Elaborating entity \"dds\" for hierarchy \"dds:inst1\"" {  } { { "mcu_sram_test.bdf" "inst1" { Schematic "F:/fpga test/mcu_sram beta1.1/mcu_sram_test.bdf" { { -144 616 840 48 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dds_lut dds:inst1\|dds_lut:inst5 " "Info: Elaborating entity \"dds_lut\" for hierarchy \"dds:inst1\|dds_lut:inst5\"" {  } { { "dds.bdf" "inst5" { Schematic "F:/fpga test/mcu_sram beta1.1/dds.bdf" { { 344 768 1000 536 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux4 dds:inst1\|dds_lut:inst5\|mux4:inst3 " "Info: Elaborating entity \"mux4\" for hierarchy \"dds:inst1\|dds_lut:inst5\|mux4:inst3\"" {  } { { "dds/dds_lut.bdf" "inst3" { Schematic "F:/fpga test/mcu_sram beta1.1/dds/dds_lut.bdf" { { 248 984 1136 360 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mux dds:inst1\|dds_lut:inst5\|mux4:inst3\|lpm_mux:lpm_mux_component " "Info: Elaborating entity \"lpm_mux\" for hierarchy \"dds:inst1\|dds_lut:inst5\|mux4:inst3\|lpm_mux:lpm_mux_component\"" {  } { { "dds/mux4.tdf" "lpm_mux_component" { Text "F:/fpga test/mcu_sram beta1.1/dds/mux4.tdf" 48 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "dds:inst1\|dds_lut:inst5\|mux4:inst3\|lpm_mux:lpm_mux_component " "Info: Elaborated megafunction instantiation \"dds:inst1\|dds_lut:inst5\|mux4:inst3\|lpm_mux:lpm_mux_component\"" {  } { { "dds/mux4.tdf" "" { Text "F:/fpga test/mcu_sram beta1.1/dds/mux4.tdf" 48 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_ogc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_ogc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_ogc " "Info: Found entity 1: mux_ogc" {  } { { "db/mux_ogc.tdf" "" { Text "F:/fpga test/mcu_sram beta1.1/db/mux_ogc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_ogc dds:inst1\|dds_lut:inst5\|mux4:inst3\|lpm_mux:lpm_mux_component\|mux_ogc:auto_generated " "Info: Elaborating entity \"mux_ogc\" for hierarchy \"dds:inst1\|dds_lut:inst5\|mux4:inst3\|lpm_mux:lpm_mux_component\|mux_ogc:auto_generated\"" {  } { { "lpm_mux.tdf" "auto_generated" { Text "f:/altera/quartus60/libraries/megafunctions/lpm_mux.tdf" 84 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram dds:inst1\|dds_lut:inst5\|ram:inst7 " "Info: Elaborating entity \"ram\" for hierarchy \"dds:inst1\|dds_lut:inst5\|ram:inst7\"" {  } { { "dds/dds_lut.bdf" "inst7" { Schematic "F:/fpga test/mcu_sram beta1.1/dds/dds_lut.bdf" { { 504 696 952 680 "inst7" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../altera/quartus60/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 426 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}