mux_ogc.tdf

verilog编写基于FPGA的示波器核心实现

--lpm_mux CASCADE_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone" IGNORE_CASCADE_BUFFERS="OFF" LPM_SIZE=4 LPM_WIDTH=12 LPM_WIDTHS=2 data result sel
--VERSION_BEGIN 6.0 cbx_lpm_mux 2006:01:09:11:16:16:SJ cbx_mgl 2006:04:14:11:14:36:SJ  VERSION_END


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--  to the terms and conditions of the Altera Program License 
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--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
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--  applicable agreement for further details.



--synthesis_resources = lut 24 
SUBDESIGN mux_ogc
( 
	data[47..0]	:	input;
	result[11..0]	:	output;
	sel[1..0]	:	input;
) 
VARIABLE 
	result_node[11..0]	: WIRE;
	sel_node[1..0]	: WIRE;
	w_data109w[3..0]	: WIRE;
	w_data134w[3..0]	: WIRE;
	w_data159w[3..0]	: WIRE;
	w_data184w[3..0]	: WIRE;
	w_data209w[3..0]	: WIRE;
	w_data234w[3..0]	: WIRE;
	w_data259w[3..0]	: WIRE;
	w_data284w[3..0]	: WIRE;
	w_data34w[3..0]	: WIRE;
	w_data4w[3..0]	: WIRE;
	w_data59w[3..0]	: WIRE;
	w_data84w[3..0]	: WIRE;
	w_result121w	: WIRE;
	w_result146w	: WIRE;
	w_result16w	: WIRE;
	w_result171w	: WIRE;
	w_result196w	: WIRE;
	w_result221w	: WIRE;
	w_result246w	: WIRE;
	w_result271w	: WIRE;
	w_result296w	: WIRE;
	w_result46w	: WIRE;
	w_result71w	: WIRE;
	w_result96w	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( (((w_data284w[1..1] & sel_node[0..0]) & (! w_result296w)) # (w_result296w & (w_data284w[3..3] # (! sel_node[0..0])))), (((w_data259w[1..1] & sel_node[0..0]) & (! w_result271w)) # (w_result271w & (w_data259w[3..3] # (! sel_node[0..0])))), (((w_data234w[1..1] & sel_node[0..0]) & (! w_result246w)) # (w_result246w & (w_data234w[3..3] # (! sel_node[0..0])))), (((w_data209w[1..1] & sel_node[0..0]) & (! w_result221w)) # (w_result221w & (w_data209w[3..3] # (! sel_node[0..0])))), (((w_data184w[1..1] & sel_node[0..0]) & (! w_result196w)) # (w_result196w & (w_data184w[3..3] # (! sel_node[0..0])))), (((w_data159w[1..1] & sel_node[0..0]) & (! w_result171w)) # (w_result171w & (w_data159w[3..3] # (! sel_node[0..0])))), (((w_data134w[1..1] & sel_node[0..0]) & (! w_result146w)) # (w_result146w & (w_data134w[3..3] # (! sel_node[0..0])))), (((w_data109w[1..1] & sel_node[0..0]) & (! w_result121w)) # (w_result121w & (w_data109w[3..3] # (! sel_node[0..0])))), (((w_data84w[1..1] & sel_node[0..0]) & (! w_result96w)) # (w_result96w & (w_data84w[3..3] # (! sel_node[0..0])))), (((w_data59w[1..1] & sel_node[0..0]) & (! w_result71w)) # (w_result71w & (w_data59w[3..3] # (! sel_node[0..0])))), (((w_data34w[1..1] & sel_node[0..0]) & (! w_result46w)) # (w_result46w & (w_data34w[3..3] # (! sel_node[0..0])))), (((w_data4w[1..1] & sel_node[0..0]) & (! w_result16w)) # (w_result16w & (w_data4w[3..3] # (! sel_node[0..0])))));
	sel_node[] = ( sel[1..0]);
	w_data109w[] = ( data[40..40], data[28..28], data[16..16], data[4..4]);
	w_data134w[] = ( data[41..41], data[29..29], data[17..17], data[5..5]);
	w_data159w[] = ( data[42..42], data[30..30], data[18..18], data[6..6]);
	w_data184w[] = ( data[43..43], data[31..31], data[19..19], data[7..7]);
	w_data209w[] = ( data[44..44], data[32..32], data[20..20], data[8..8]);
	w_data234w[] = ( data[45..45], data[33..33], data[21..21], data[9..9]);
	w_data259w[] = ( data[46..46], data[34..34], data[22..22], data[10..10]);
	w_data284w[] = ( data[47..47], data[35..35], data[23..23], data[11..11]);
	w_data34w[] = ( data[37..37], data[25..25], data[13..13], data[1..1]);
	w_data4w[] = ( data[36..36], data[24..24], data[12..12], data[0..0]);
	w_data59w[] = ( data[38..38], data[26..26], data[14..14], data[2..2]);
	w_data84w[] = ( data[39..39], data[27..27], data[15..15], data[3..3]);
	w_result121w = (((w_data109w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data109w[2..2])));
	w_result146w = (((w_data134w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data134w[2..2])));
	w_result16w = (((w_data4w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data4w[2..2])));
	w_result171w = (((w_data159w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data159w[2..2])));
	w_result196w = (((w_data184w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data184w[2..2])));
	w_result221w = (((w_data209w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data209w[2..2])));
	w_result246w = (((w_data234w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data234w[2..2])));
	w_result271w = (((w_data259w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data259w[2..2])));
	w_result296w = (((w_data284w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data284w[2..2])));
	w_result46w = (((w_data34w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data34w[2..2])));
	w_result71w = (((w_data59w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data59w[2..2])));
	w_result96w = (((w_data84w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data84w[2..2])));
END;
--VALID FILE