mcu_sram_test.map.qmsg

verilog编写基于FPGA的示波器核心实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 18 15:03:12 2007 " "Info: Processing started: Wed Jul 18 15:03:12 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off mcu_sram_test -c mcu_sram_test " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mcu_sram_test -c mcu_sram_test" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mux_sram.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mux_sram.v" { { "Info" "ISGN_ENTITY_NAME" "1 mux_sram " "Info: Found entity 1: mux_sram" {  } { { "mux_sram.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/mux_sram.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dds/lpm_add_sub0.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dds/lpm_add_sub0.v" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub0 " "Info: Found entity 1: lpm_add_sub0" {  } { { "dds/lpm_add_sub0.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/dds/lpm_add_sub0.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dds/add.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dds/add.v" { { "Info" "ISGN_ENTITY_NAME" "1 add " "Info: Found entity 1: add" {  } { { "dds/add.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/dds/add.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dds/square.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file dds/square.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 square " "Info: Found entity 1: square" {  } { { "dds/square.tdf" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/dds/square.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dds/cos_rom.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file dds/cos_rom.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cos_rom " "Info: Found entity 1: cos_rom" {  } { { "dds/cos_rom.tdf" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/dds/cos_rom.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dds/dds_lut.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file dds/dds_lut.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 dds_lut " "Info: Found entity 1: dds_lut" {  } { { "dds/dds_lut.bdf" "" { Schematic "F:/fpga test/fpge示波器/mcu_sram beta1.1/dds/dds_lut.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dds/mux4.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file dds/mux4.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux4 " "Info: Found entity 1: mux4" {  } { { "dds/mux4.tdf" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/dds/mux4.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dds/ram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file dds/ram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 ram " "Info: Found entity 1: ram" {  } { { "dds/ram.tdf" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/dds/ram.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dds/sin_rom.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file dds/sin_rom.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sin_rom " "Info: Found entity 1: sin_rom" {  } { { "dds/sin_rom.tdf" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/dds/sin_rom.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mcu_sram_test.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file mcu_sram_test.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 mcu_sram_test " "Info: Found entity 1: mcu_sram_test" {  } { { "mcu_sram_test.bdf" "" { Schematic "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_sram_test.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "mcu_fpga_control.v(80) " "Warning (10273): Verilog HDL warning at mcu_fpga_control.v(80): extended using \"x\" or \"z\"" {  } { { "mcu_fpga_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_fpga_control.v" 80 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "mcu_fpga_control.v(81) " "Warning (10273): Verilog HDL warning at mcu_fpga_control.v(81): extended using \"x\" or \"z\"" {  } { { "mcu_fpga_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_fpga_control.v" 81 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mcu_fpga_control.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mcu_fpga_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 mcu_fpga_control " "Info: Found entity 1: mcu_fpga_control" {  } { { "mcu_fpga_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/mcu_fpga_control.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "sram_control.v(69) " "Warning (10273): Verilog HDL warning at sram_control.v(69): extended using \"x\" or \"z\"" {  } { { "sram_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/sram_control.v" 69 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "sram_control.v(70) " "Warning (10273): Verilog HDL warning at sram_control.v(70): extended using \"x\" or \"z\"" {  } { { "sram_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/sram_control.v" 70 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "sram_control.v(71) " "Warning (10273): Verilog HDL warning at sram_control.v(71): extended using \"x\" or \"z\"" {  } { { "sram_control.v" "" { Text "F:/fpga test/fpge示波器/mcu_sram beta1.1/sram_control.v" 71 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}