📄 osc_disp.vwf

📁 verilog编写基于FPGA的示波器核心实现
💻 VWF
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	PRINT_OPTIONS = "Print_options_version 6\
range_start 0ps\
range_end 1.0us\
width 1\
names_percentage 25\
comments 1\
grid_lines 1\
time_bars 1\
name_every_page 0\
expand_groups 0\
print_all 1";
	SIMULATION_TIME = 100000.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 10.0;
	GRID_DUTY_CYCLE = 50;
}

SIGNAL("RDADDR")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 10;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("RDADDR[9]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "RDADDR";
}

SIGNAL("RDADDR[8]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "RDADDR";
}

SIGNAL("RDADDR[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "RDADDR";
}

SIGNAL("RDADDR[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "RDADDR";
}

SIGNAL("RDADDR[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "RDADDR";
}

SIGNAL("RDADDR[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "RDADDR";
}

SIGNAL("RDADDR[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "RDADDR";
}

SIGNAL("RDADDR[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "RDADDR";
}

SIGNAL("RDADDR[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "RDADDR";
}

SIGNAL("RDADDR[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "RDADDR";
}

SIGNAL("clk")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("cs")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("datain")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 8;
	LSB_INDEX = 0;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("datain[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "datain";
}

SIGNAL("datain[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "datain";
}

SIGNAL("datain[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "datain";
}

SIGNAL("datain[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "datain";
}

SIGNAL("datain[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "datain";
}

SIGNAL("datain[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "datain";
}

SIGNAL("datain[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "datain";
}

SIGNAL("datain[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "datain";
}

SIGNAL("x_out")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 8;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("x_out[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "x_out";
}

SIGNAL("x_out[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "x_out";
}

SIGNAL("x_out[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "x_out";
}

SIGNAL("x_out[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "x_out";
}

SIGNAL("x_out[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "x_out";
}

SIGNAL("x_out[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "x_out";
}

SIGNAL("x_out[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "x_out";
}

SIGNAL("x_out[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "x_out";
}

SIGNAL("y_out")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 8;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("y_out[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "y_out";
}

SIGNAL("y_out[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "y_out";
}

SIGNAL("y_out[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "y_out";
}

SIGNAL("y_out[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "y_out";
}

SIGNAL("y_out[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "y_out";
}

SIGNAL("y_out[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "y_out";
}

SIGNAL("y_out[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "y_out";
}

SIGNAL("y_out[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "y_out";
}

TRANSITION_LIST("RDADDR[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("RDADDR[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000.0;
	}
}

TRANSITION_LIST("RDADDR[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 30755.625;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 30.0;
			LEVEL 0 FOR 30720.0;
		}
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 7714.375;
	}
}

TRANSITION_LIST("RDADDR[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 15394.801;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 15360.0;
			LEVEL 0 FOR 15390.0;
		}
		LEVEL 1 FOR 15360.0;
		LEVEL 0 FOR 7745.199;
	}
}

TRANSITION_LIST("RDADDR[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 7713.658;
		NODE
		{
			REPEAT = 3;
			LEVEL 1 FOR 7680.0;
			LEVEL 0 FOR 7680.0;
			LEVEL 1 FOR 7680.0;
			LEVEL 0 FOR 7710.0;
		}
		LEVEL 1 FOR 36.342;
	}
}

TRANSITION_LIST("RDADDR[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 3872.954;
		NODE
		{
			REPEAT = 2;
			NODE
			{
				REPEAT = 3;
				LEVEL 1 FOR 3840.0;
				LEVEL 0 FOR 3840.0;
			}
			LEVEL 1 FOR 3840.0;
			LEVEL 0 FOR 3870.0;
		}
		NODE
		{
			REPEAT = 3;
			LEVEL 1 FOR 3840.0;
			LEVEL 0 FOR 3840.0;
		}
		LEVEL 1 FOR 3840.0;
		LEVEL 0 FOR 3870.0;
		LEVEL 1 FOR 3840.0;
		LEVEL 0 FOR 37.046;
	}
}

TRANSITION_LIST("RDADDR[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1952.65;
		NODE
		{
			REPEAT = 2;
			NODE
			{
				REPEAT = 7;
				LEVEL 1 FOR 1920.0;
				LEVEL 0 FOR 1920.0;
			}
			LEVEL 1 FOR 1920.0;
			LEVEL 0 FOR 1950.0;
		}
		NODE
		{
			REPEAT = 7;
			LEVEL 1 FOR 1920.0;
			LEVEL 0 FOR 1920.0;
		}
		LEVEL 1 FOR 1920.0;
		LEVEL 0 FOR 1950.0;
		LEVEL 1 FOR 1920.0;
		LEVEL 0 FOR 1920.0;
		LEVEL 1 FOR 1920.0;
		LEVEL 0 FOR 37.35;
	}
}

TRANSITION_LIST("RDADDR[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 992.54;
		NODE
		{
			REPEAT = 2;
			NODE
			{
				REPEAT = 15;
				LEVEL 1 FOR 960.0;
				LEVEL 0 FOR 960.0;
			}
			LEVEL 1 FOR 960.0;
			LEVEL 0 FOR 990.0;
		}
		NODE
		{
			REPEAT = 15;
			LEVEL 1 FOR 960.0;
			LEVEL 0 FOR 960.0;
		}
		LEVEL 1 FOR 960.0;
		LEVEL 0 FOR 990.0;
		NODE
		{
			REPEAT = 3;
			LEVEL 1 FOR 960.0;
			LEVEL 0 FOR 960.0;
		}
		LEVEL 1 FOR 960.0;
		LEVEL 0 FOR 37.46;
	}
}

TRANSITION_LIST("RDADDR[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 512.542;
		NODE
		{
			REPEAT = 2;
			NODE
			{
				REPEAT = 31;
				LEVEL 1 FOR 480.0;
				LEVEL 0 FOR 480.0;
			}
			LEVEL 1 FOR 480.0;
			LEVEL 0 FOR 510.0;
		}
		NODE
		{
			REPEAT = 31;
			LEVEL 1 FOR 480.0;
			LEVEL 0 FOR 480.0;
		}
		LEVEL 1 FOR 480.0;
		LEVEL 0 FOR 510.0;
		NODE
		{
			REPEAT = 7;
			LEVEL 1 FOR 480.0;
			LEVEL 0 FOR 480.0;
		}
		LEVEL 1 FOR 480.0;
		LEVEL 0 FOR 37.458;
	}
}

TRANSITION_LIST("RDADDR[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 272.77;
		NODE
		{
			REPEAT = 2;
			NODE
			{
				REPEAT = 63;
				LEVEL 1 FOR 240.0;
				LEVEL 0 FOR 240.0;
			}
			LEVEL 1 FOR 240.0;
			LEVEL 0 FOR 270.0;
		}
		NODE
		{
			REPEAT = 63;
			LEVEL 1 FOR 240.0;
			LEVEL 0 FOR 240.0;
		}
		LEVEL 1 FOR 240.0;
		LEVEL 0 FOR 270.0;
		NODE
		{
			REPEAT = 15;
			LEVEL 1 FOR 240.0;
			LEVEL 0 FOR 240.0;
		}
		LEVEL 1 FOR 240.0;
		LEVEL 0 FOR 37.23;
	}
}

TRANSITION_LIST("clk")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10000;
			LEVEL 0 FOR 5.0;
			LEVEL 1 FOR 5.0;
		}
	}
}

TRANSITION_LIST("cs")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 99980.0;
	}
}

TRANSITION_LIST("datain[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 280.0;
		NODE
		{
			REPEAT = 99;
			LEVEL 1 FOR 250.0;
			LEVEL 0 FOR 750.0;
		}
		LEVEL 1 FOR 250.0;
		LEVEL 0 FOR 470.0;
	}
}

TRANSITION_LIST("datain[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 30.0;
		NODE
		{
			REPEAT = 99;
			LEVEL 1 FOR 500.0;
			LEVEL 0 FOR 500.0;
		}
		LEVEL 1 FOR 500.0;
		LEVEL 0 FOR 470.0;
	}
}

TRANSITION_LIST("datain[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 280.0;
		NODE
		{
			REPEAT = 99;
			LEVEL 1 FOR 250.0;
			LEVEL 0 FOR 750.0;
		}
		LEVEL 1 FOR 250.0;
		LEVEL 0 FOR 470.0;
	}
}

TRANSITION_LIST("datain[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 30.0;
		NODE
		{
			REPEAT = 99;
			LEVEL 1 FOR 500.0;
			LEVEL 0 FOR 500.0;
		}
		LEVEL 1 FOR 500.0;
		LEVEL 0 FOR 470.0;
	}
}

TRANSITION_LIST("datain[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 280.0;
		NODE
		{
			REPEAT = 99;
			LEVEL 1 FOR 250.0;
			LEVEL 0 FOR 750.0;
		}
		LEVEL 1 FOR 250.0;
		LEVEL 0 FOR 470.0;
	}
}

TRANSITION_LIST("datain[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 30.0;
		NODE
		{
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💿 文件大小 992 K
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