sun.mif

verilog编写基于FPGA的示波器核心实现

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- Quartus II generated Memory Initialization File (.mif)

WIDTH=8;
DEPTH=1024;

ADDRESS_RADIX=UNS;
DATA_RADIX=UNS;

CONTENT BEGIN
	[0..16]  :   0;
	17    :   32;
	18    :   64;
	[19..32]  :   0;
	33    :   80;
	34    :   160;
	[35..48]  :   0;
	49    :   16;
	50    :   32;
	[51..64]  :   0;
	65    :   16;
	66    :   32;
	[67..80]  :   0;
	81    :   20;
	82    :   34;
	[83..96]  :   0;
	97    :   146;
	98    :   34;
	[99..112]  :   0;
	113   :   82;
	114   :   34;
	[115..128]  :   0;
	129   :   49;
	130   :   36;
	[131..144]  :   0;
	145   :   29;
	146   :   164;
	[147..160]  :   0;
	161   :   17;
	162   :   40;
	[163..176]  :   0;
	177   :   16;
	178   :   32;
	[179..192]  :   0;
	193   :   8;
	194   :   32;
	[195..208]  :   0;
	209   :   4;
	210   :   32;
	[211..224]  :   0;
	225   :   126;
	226   :   32;
	[227..241]  :   0;
	242   :   32;
	[243..1023]  :   0;
END;