osc.bsf

verilog编写基于FPGA的示波器核心实现

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
	(rect 16 16 200 176)
	(text "osc" (rect 5 0 26 14)(font "Arial" (font_size 8)))
	(text "inst" (rect 8 144 25 156)(font "Arial" ))
	(port
		(pt 0 32)
		(input)
		(text "osc_dis_cs" (rect 0 0 66 14)(font "Arial" (font_size 8)))
		(text "osc_dis_cs" (rect 21 27 87 41)(font "Arial" (font_size 8)))
		(line (pt 0 32)(pt 16 32)(line_width 1))
	)
	(port
		(pt 0 48)
		(input)
		(text "addrin[16..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
		(text "addrin[16..0]" (rect 21 43 91 57)(font "Arial" (font_size 8)))
		(line (pt 0 48)(pt 16 48)(line_width 3))
	)
	(port
		(pt 0 64)
		(input)
		(text "datain[15..0]" (rect 0 0 69 14)(font "Arial" (font_size 8)))
		(text "datain[15..0]" (rect 21 59 90 73)(font "Arial" (font_size 8)))
		(line (pt 0 64)(pt 16 64)(line_width 3))
	)
	(port
		(pt 0 80)
		(input)
		(text "oscsig" (rect 0 0 37 14)(font "Arial" (font_size 8)))
		(text "oscsig" (rect 21 75 58 89)(font "Arial" (font_size 8)))
		(line (pt 0 80)(pt 16 80)(line_width 1))
	)
	(port
		(pt 0 96)
		(input)
		(text "cs" (rect 0 0 14 14)(font "Arial" (font_size 8)))
		(text "cs" (rect 21 91 35 105)(font "Arial" (font_size 8)))
		(line (pt 0 96)(pt 16 96)(line_width 1))
	)
	(port
		(pt 0 112)
		(input)
		(text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
		(text "clk" (rect 21 107 36 121)(font "Arial" (font_size 8)))
		(line (pt 0 112)(pt 16 112)(line_width 1))
	)
	(port
		(pt 0 128)
		(input)
		(text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8)))
		(text "rdclk" (rect 21 123 48 137)(font "Arial" (font_size 8)))
		(line (pt 0 128)(pt 16 128)(line_width 1))
	)
	(port
		(pt 184 32)
		(output)
		(text "x_da[7..0]" (rect 0 0 56 14)(font "Arial" (font_size 8)))
		(text "x_da[7..0]" (rect 107 27 163 41)(font "Arial" (font_size 8)))
		(line (pt 184 32)(pt 168 32)(line_width 3))
	)
	(port
		(pt 184 48)
		(output)
		(text "y_da[7..0]" (rect 0 0 56 14)(font "Arial" (font_size 8)))
		(text "y_da[7..0]" (rect 107 43 163 57)(font "Arial" (font_size 8)))
		(line (pt 184 48)(pt 168 48)(line_width 3))
	)
	(port
		(pt 184 64)
		(output)
		(text "da_wrx" (rect 0 0 44 14)(font "Arial" (font_size 8)))
		(text "da_wrx" (rect 119 59 163 73)(font "Arial" (font_size 8)))
		(line (pt 184 64)(pt 168 64)(line_width 1))
	)
	(port
		(pt 184 80)
		(output)
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		(text "da_wry" (rect 119 75 163 89)(font "Arial" (font_size 8)))
		(line (pt 184 80)(pt 168 80)(line_width 1))
	)
	(drawing
		(rectangle (rect 16 16 168 144)(line_width 1))
	)
)